Data Word Formats - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers
• Low receive frame sync select. (
(if set) or active high
RFS
• Late receive frame sync. (
syncs (if set) or early frame syncs (if cleared).
• Clock drive/sample edge select. (
edge of the
for sampling externally generated frame syncs, and for driving
internally generated frame syncs. If set, internally generated frame
syncs are driven on the falling edge, and data and externally gener-
ated frame syncs are sampled on the rising edge. If cleared,
internally generated frame syncs are driven on the rising edge, and
data and externally generated frame syncs are sampled on the fall-
ing edge.
• RxSec enable. (
the SPORT (if set).
• Stereo serial enable. (
ating mode of the SPORT (if set). By default this bit is cleared,
enabling normal clocking and frame sync.
• Left/Right order. (
received first in stereo serial operating mode. By default this bit is
cleared, and the left channel is received first.

Data Word Formats

The format of the data words transferred over the SPORTs is configured
by the combination of transmit
; and
RLSBIT TLSBIT
registers.
SPORT_RCR2
19-56
RFS
LARFS
clock signal the SPORT uses for sampling data,
RSCLK
). This bit enables the receive secondary side of
RXSE
). This bit enables the stereo serial oper-
RSFSE
). If this bit is set, the right channel is
RRFST
SLEN
bits of the
SPORT_TCR1
ADSP-BF50x Blackfin Processor Hardware Reference
). This bit selects an active low
LRFS
(if cleared).
). This bit configures late frame
). This bit selects which
RCKFE
and receive
SLEN; RDTYPE
,
SPORT_TCR2
; ;
TDTYPE
, , and
SPORT_RCR1