Interface Overview; External Interface; Internal Interface - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

Figure 12-1 provides a block diagram of the watchdog timer.
WDOG_CNT
32
WDOG_STAT
SCLK
Figure 12-1. Watchdog Timer Block Diagram

External Interface

The watchdog timer does not directly interact with any pins of the chip.

Internal Interface

The watchdog timer is clocked by the system clock
accessed through the 16-bit peripheral access bus (PAB). The 32-bit regis-
ters and
WDOG_CNT
operations. Hardware ensures that those accesses are atomic.
ADSP-BF50x Blackfin Processor Hardware Reference
RELOAD
READ
must always be accessed by 32-bit read/write
WDOG_STAT
Watchdog Timer
PAB
16
WDEN
WDRO
WRITE
EXPIRE
SCLK
WDOG_CTL
WDEV
RESET
EVENT
NMI
CONTROL
IRQ
. Its registers are
12-3