Analog Devices ADSP-BF506F Hardware Reference Manual page 817

Adsp-bf50x blackfin processor

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Figure 18-5. SPI Modes of Operation

The clock polarity and the clock phase should be identical for the master

device and the slave device involved in the communication link. The

transfer format from the master may be changed between transfers to

adjust to various requirements of a slave device.

= 0, the slave select line,

between each serial transfer. This is controlled automatically by the SPI

hardware logic. When

between successive transfers or be inactive (high). This must be controlled

by the software through manipulation of the

ADSP-BF50x Blackfin Processor Hardware Reference

CLOCK PHASE (CPHA)

SPI-Compatible Port Controller

, must be inactive (high)

may either remain active (low)

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