Mode Bits (Polarity And Srmode); Output Enable Function - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description

Mode Bits (POLARITY and SRMODE)

PWM_POLARITY
register.

The incorrect programming of these two mode-select signals can
have destructive consequences on the external power inverter con-
nected to the PWM unit. Since
software programmable bits, accidental power inverter
shoot-through current may occur from incorrect programming.

Output Enable Function

The register also contains six bits (bits 0 to 5) that can be used to
PWM_SEG
individually enable or disable each of the six PWM outputs. The PWM
signal of the
AL
ister, the
AH_EN
controls , the
BH
output. If the associated bit of the
ing PWM output is disabled irrespective of the value of the corresponding
duty cycle register. This PWM output signal will remain in the off state as
long as the corresponding enable/disable bit of the
This output enable function is implemented after the crossover function.
Following a reset, all six enable bits of the
that all PWM outputs are enabled by default. In a manner identical to the
duty cycle registers, the
the signal so that changes to this register only become effective
PWM_SYNC
at the start of each PWM cycle in single-update mode. In double-update
mode, the
PWM_SEG
PWM cycle.
14-26
and are programmable bits of the
PWM_SRMODE
pin is enabled by clearing the
bit controls , the
AH
bit controls
CL_EN
PWM_SEG
register can also be updated at the midpoint of the
ADSP-BF50x Blackfin Processor Hardware Reference
PWM_POLARITY
AL_EN
bit controls
BL_EN
, and the
CL CH_EN
register is set, the correspond-
PWM_SEG
PWM_SEG
register is latched on the rising edge of
PWM_CTRL
and
PWM_SRMODE
bit of the
PWM_SEG
, the bit
BL BH_EN
bit controls the
CH
register is set.
PWM_SEG
register are cleared so
are
reg-