L1 Instruction Sram - Analog Devices ADSP-BF506F Hardware Reference Manual

L1 Instruction SRAM

0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA0 8000
0xFFA0 4000
0xFFA0 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 1000
0xEF00 0000
0x2040 0000
0x2000 0000
0x0000 0000
Figure 2-1. ADSP-BF50x Memory Map
L1 Instruction SRAM
The processor core reads the instruction memory through the 64-bit wide
instruction fetch bus. All addresses from this bus are 64-bit aligned. Each
instruction fetch can return any combination of 16-, 32-, or 64-bit
instructions (for example, four 16-bit instructions, two 16-bit instructions
and one 32-bit instruction, or one 64-bit instruction).
2-2
CORE MEMORY MAPPED REGISTERS
SYSTEM MEMORY MAPPED REGISTERS
RESERVED
INTERNAL SCRATCHPAD RAM (4K BYTES)
RESERVED
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K BYTES)
L1 INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K BYTES)
L1 DATA BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (4K BYTES)
RESERVED
SYNC FLASH (32M BITS) *
RESERVED
* AVAILABLE ON PARTS WITH SYNC FLASH (F)
ADSP-BF50x Blackfin Processor Hardware Reference