Pab Arbitration; Pab Agents (Masters, Slaves) - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview
The core processor has byte addressability, but the programming model is
restricted to only 32-bit (aligned) access to the system MMRs. Byte
accesses to this region are not supported.

PAB Arbitration

The core is the only master on this bus. No arbitration is necessary.

PAB Agents (Masters, Slaves)

The processor core can master bus operations on the PAB. All peripherals
have a peripheral bus slave interface which allows the core to access con-
trol and status state. These registers are mapped into the system MMR
space of the memory map. For the register addresses, see
Assignments" on page
The slaves on the PAB bus are:
• System event controller
• Clock and power management controller
• Watchdog timer
• Counters
• Timer 0–7
• SPORT0–1
• SPI0–1
• Ports
• UART0–1
• PPI
• TWI
3-6
A-1.
ADSP-BF50x Blackfin Processor Hardware Reference
"System MMR