External Access Bus (Eab); Arbitration Of The External Bus; Deb/Eab Performance - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview
DMA access to L1 memory can only be stalled by an access already in
progress from another DMA channel. Latencies caused by these stalls are
in addition to any arbitration latencies.

The core processor and the DAB must arbitrate for access to exter-
nal memory through the EBIU. This additional arbitration latency
added to the latency required to read off-chip memory devices can
significantly degrade DAB throughput, potentially causing periph-
eral data buffers to underflow or overflow. If you use DMA
peripherals other than the memory DMA controller, and you target
external memory for DMA accesses, you need to carefully analyze
your specific traffic patterns. Make sure that isochronous peripher-
als targeting internal memory have enough allocated bandwidth
and the appropriate maximum arbitration latencies.

External Access Bus (EAB)

The EAB provides a way for the processor core to directly access off-chip
memory.

Arbitration of the External Bus

Arbitration for use of external port bus interface resources is required
because of possible contention between the potential masters of this bus. A
fixed-priority arbitration scheme is used. That is, core accesses via the
EAB will be of higher priority than those from the DMA external bus
(DEB).

DEB/EAB Performance

The DEB and the EAB support single word accesses of either 8-bit or
16-bit data types. The DEB and the EAB operate at the same frequency as
the PAB and the DAB, up to the maximum
the processor data sheet.
3-10 ADSP-BF50x Blackfin Processor Hardware Reference
frequency specified in
SCLK