Rsi Data Length Register (Rsi_Data_Lgth) - Analog Devices ADSP-BF506F Hardware Reference Manual

RSI Registers

RSI Data Length Register (RSI_DATA_LGTH)

The
RSI_DATA_LGTH
bytes to be transferred before setting the
register. The value loaded to this register is copied into the
register when the data path state machine is enabled and starts the
transfer.
RSI Data Length Register (RSI_DATA_LGTH)
Read
0xFFC0 3828
15 14 13 12 11 10
0
DATA_LENGTH
Figure 21-13. RSI Data Length Register
Table 21-17. RSI_DATA_LGTH Register
Bit Name
15:0 DATA_LENGTH
RSI Data Control Register (RSI_DATA_CONTROL)
The
RSI_DATA_CONTROL
machine. The state machine becomes enabled once the
The direction of the transfer is determined by
channel is to be used for the data transfer, the
set; otherwise, the RSI FIFO is only accessible via the core. For block
transfers, the block length must be specified via
block length is 2
in this register configure the behavior of the command path state machine
for communication with CE-ATA devices. After a data write, data cannot
be written to this register for five
21-62
register contains a 16-bit value for the number of data
9 8 7
0 0 0 0 0 0 0 0
Function
Number of bytes to be transferred
register largely controls the data path state
DATA_BLK_LGTH
. Two bits (
SCLK
ADSP-BF50x Blackfin Processor Hardware Reference
flag of the
DAT_END
6 5 4 3 2 1 0
0 0 0 0 0 0 0
DATA_DIR
DATA_DMA_EN
DATA_BLK_LGTH
CEATA_CCS_EN
cycles.
RSI_STATUS
RSI_DATA_CNT
Reset = 0x0000
Type Default
R/W 0
bit is set.
DATA_EN
. If the DMA
bit must be
, where the
and )
CEATA_EN