Ebiu_Amgctl Register - Analog Devices ADSP-BF506F Hardware Reference Manual

EBIU Registers

EBIU_AMGCTL Register

Figure 5-3 shows the asynchronous memory global control register
( ).
EBIU_AMGCTL
Asynchronous Memory Global Control Register (EBIU_AMGCTL)
15 14 13 12 11 10
0xFFC0 0A00
0 0
CDPRIO
0 - Core has priority over DMA
for external accesses
1 - DMA has priority over core
for external accesses
For more information, please see
Chapter 3, "Chip Bus
Figure 5-3. Asynchronous Memory Global Control Register
5-10
9 8 7
0 0 0 0 0 0 1
Hierarchy".
ADSP-BF50x Blackfin Processor Hardware Reference
6 5 4 3 2 1 0
1 1 1 0 0 1 1
AMCKEN
0 - Disable CLKOUT for
1 - Enable CLKOUT for
AMBEN
Enable Flash memory bank
0 - Flash bank disabled
1 - Flash bank enabled
Reset = 0x00F3
asynchronous memory
region accesses
asynchronous memory
region accesses