Sport Multichannel Configuration (Sport_Mcmc1 And Sport_Mcmc2) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Receive Frame Sync Divider Register (SPORT_RFSDIV)
15 14 13 12 11 10
0 0 0 0 0 0
Figure 19-37. SPORT Receive Frame Sync Divider Register
SPORT Multichannel Configuration
(SPORT_MCMC1 and SPORT_MCMC2) Registers
There are two multichannel configuration registers for each SPORT,
shown in Figure 19-38
figure the multichannel operation of the SPORT. The two control
registers are shown below.
SPORT Multichannel Configuration Register 1 (SPORT_MCMC1)
15 14 13 12 11 10
0
WSIZE[3:0] (Window Size)
Value in field = [(Desired window size)/8 –1]
Figure 19-38. SPORT Multichannel Configuration Register 1
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7 6 5 4 3
0 0 0 0 0 0 0
Frame Sync Divider[15:0]
Number of receive clock cycles counted
before generating RFS pulse
and Figure
9 8 7
0 0 0 0 0 0 0 0
2 1 0
Reset = 0x0000
0 0 0
19-39. These registers are used to con-
6 5 4 3 2 1 0
0 0 0 0 0 0 0
WOFF[9:0] (Window Offset)
Places start of window anywhere in
the 0 to 1023 channel range
SPORT Controller
Reset = 0x0000
19-65