Watchdog Control (Wdog_Ctl) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

The
WDOG_STAT
accessed with 32-bit reads and writes.
Watchdog Status Register (WDOG_STAT)
31 30 29 28 27 26
0 0 0 0 0
15 14 13 12 11 10
0 0 0 0 0 0
Figure 12-3. Watchdog Status Register

Watchdog Control (WDOG_CTL) Register

The WDOG_CTL register, shown in
MMR used to control the watchdog timer.
The watchdog event (
generated when the watchdog timer expires. Note that if the general-pur-
pose interrupt option is selected, the
watchdog timer mask bit should be appropriately configured to unmask
that interrupt. If the generation of watchdog events is disabled, the watch-
dog timer operates as described, except that no event is generated when
the watchdog timer expires.
The watchdog enable (
the watchdog timer. Writing any value other than the disable key (0xAD)
into this field enables the watchdog timer. This multibit disable key mini-
mizes the chance of inadvertently disabling the watchdog timer.
Software can determine whether the watchdog has expired by interrogat-
ing the status bit of the
WDRO
ADSP-BF50x Blackfin Processor Hardware Reference
register is a 32-bit unsigned system MMR that must be
25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
9 8 7 6 5 4 3
0 0 0 0 0 0 0
) bit field is used to select the event that is
WDEV[1:0]
WDEN[7:0]
WDOG_CTL
0 0 0 Reset = 0x0000 0000
Watchdog Status[31:16]
2 1 0
0 0 0
Watchdog Status[15:0]
Figure 12-4, is a 16-bit system
register that holds the
SIC_IMASK
) bit field is used to enable and disable
register. This is a sticky bit that is
Watchdog Timer
12-7