Analog Devices ADSP-BF506F Hardware Reference Manual page 834

Programming Model
WRITE TO PORT REGISTERS TO ENABLE
AND SELECT THE APPROPRIATE SLAVE
SELECT SIGNALS.
WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS
WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE
WRITE SPI_FLG
TO SELECT SLAVE(S)
USING FLGx BITS
WRITE SPI_TBDR WITH DATA TO SEND OVER SPI
READ SPI_RDBR
READ NEW DATA
FROM SPI_RDBR
Figure 18-8. Core-Driven SPI Flow Chart
18-30
Y
MULTISLAVE
SUPPORT?
MSTR = 1
WRITE SPI_CTL TO CONFIGURE SPI HARDWARE AND ENABLE SPI PORT
Y
Y
TO START
TRANSFER
WAIT FOR TRANSFER COMPLETE
LAST TRANSFER?
N
Y
TIMOD = 01
N
ADSP-BF50x Blackfin Processor Hardware Reference
WRITE TO PORT REGISTERS TO ENABLE SPI
SIGNALS AND SELECT THE REQUIRED SIGNALS.
MASTER
MASTER OR SLAVE?
N
CPHA = 1
AND
MSTR = 1
N
TIMOD = 00
N
CPHA = 1
Y
AND
MSTR = 1
N
WRITE SPI_CTL TO DISABLE SPI PORT
SLAVE, MSTR = 0
WRITE SPI_FLG
Y
TO DESELECT
SLAVE(S) USING
FLGx BITS