Analog Devices ADSP-BF506F Hardware Reference Manual page 146

Overview
Table 6-1. EBIU/Internal Flash Memory Internal Pin Connections
EBIU Pins
A21-A1
D15-D0
AMS0
ARE
ADV
NOR_CLK
ARDY
AWE
—
RP 1
V PP 1
1 These are controlled through the internal flash memory control register. See
Memory Control (FLASH_CONTROL) Register" on page
The ADSP-BF50xF processors contain an internal flash memory. It is a
32M bit (2M bit × 16) non-volatile flash memory. The internal flash
memory can be erased electrically at block level and programmed in-sys-
tem on a word-by-word basis using a 1.7 V to 2 V
the circuitry and a 2.7 V to 3.3 V
pins. Figure 6-1
memory.
6-2
Stacked Flash Pins
A20-A0
D15-D0
E
G
L
K
WAIT
W
WP
RP
V PP
V
and Table 6-2 show the internal connections to the flash
ADSP-BF50x Blackfin Processor Hardware Reference
Comment
Address pins
Data
Chip enable
Output enable
Latch enable (address valid)
Burst clock
Wait
Write enable
Write protect (tied low)
Reset
Global program/erase protect
6-88.
V
DDFLASH
supply for the input/output
DDFLASH
"Internal Flash
supply for