Analog Devices ADSP-BF506F Hardware Reference Manual page 567

count direction changes, and the unit increments from -PWMTM/2 to
the +PWMTM/2 value.
PWMTM÷2
–PWMTM÷2
PWM_SYNC_OUT
SINGLE-UPDATE MODE
PWM_SYNC_OUT
DOUBLE_UPDATE MODE
PWM_PHASE
Figure 14-6. Operation of Internal PWM Timer
Figure 14-6 also shows the PWM SYNC pulses during single-update
mode and double-update mode. Clearly, an additional PWM SYNC pulse
is generated at the midpoint of the PWM cycle in double-update mode. If
the value of the
mode, the duration of the second half period (when the
the register is set) may differ from that of the first half cycle.
PWM_STAT
is double-buffered; a change in one half of the PWM switching
PWM_TM
period will only take effect in the next half period.
ADSP-BF50x Blackfin Processor Hardware Reference
PWM TIMER DECREMENTS FROM
PWMTM÷2 TO –PWMTM÷2
register is altered at the midpoint in double-update
PWM_TM
PWM Controller
PWM TIMER INCREMENTS FROM
–PWMTM÷2 TO PWMTM÷2
1
t
C K
PWM_PHASE
bit of
14-23