Analog Devices ADSP-BF506F Hardware Reference Manual page 680

Register Descriptions
During and at the conclusion of register slave mode transfers, the
TWI_SLAVE_STAT
ally slave mode status bits are not associated with the generation of
interrupts. Master mode operation does not affect slave mode status bits.
• General call (
This bit self clears if slave mode is disabled (
[0] At the time of addressing, the address was not determined to be
a general call.
[1] At the time of addressing, the address was determined to be a
general call.
• Slave transfer direction (
This bit self clears if slave mode is disabled (
[0] At the time of addressing, the transfer direction was determined
to be slave receive.
[1] At the time of addressing, the transfer direction was determined
to be slave transmit.
16-30
register holds information on the current transfer. Gener-
)
GCALL
SDIR
ADSP-BF50x Blackfin Processor Hardware Reference
SEN
)
SEN
= 0).
= 0).