Configuring Internal Flash Memory For Synchronous Burst Read Mode - Analog Devices ADSP-BF506F Hardware Reference Manual

page 6-7 for information on flash commands including the block unlock
command.
Configuring Internal Flash Memory for
Synchronous Burst Read Mode
In order to operate the internal flash device in synchronous burst mode,
both the internal flash device and the EBIU have to be set in synchronous
mode. The internal flash device is set in synchronous burst mode through
the use of the Set Configuration Register command. The EBIU is set in
synchronous mode by programming the
register to the value
in the EBIU registers as shown in section
chronous Read Mode" on page
As shown in Table 6-5 (Standard
required to issue the Set Configuration Register command.
The first cycle writes the setup command to the address corresponding to
the value that is to be programmed into the configuration register. The
second cycle writes the confirm command to the address corresponding to
the value that is to be programmed into the configuration register.
For both cycles, the address corresponding to the value that is to be pro-
grammed into the configuration register is:
FLASH_BASE_ADDRESS
where:
FLASH_BASE_ADDRESS
BF50x devices, this address is 0x20000000 and
is the value to be programmed into the flash's configuration
value
register.
ADSP-BF50x Blackfin Processor Hardware Reference
and by programming the timing configurations
b#11
6-85.
Commands), two write cycles are
+ (
configuration_register_value
is the base address of the flash device. On ADSP-
Internal Flash Memory
field in the
B0MODE
"Configuring the EBIU for Syn-
<< 1)
configuration_register_
EBIU_MODECTL
6-83