Twi Fifo Status Register (Twi_Fifo_Stat); Twi Fifo Status - Analog Devices ADSP-BF506F Hardware Reference Manual

Register Descriptions
• Transmit buffer flush (
[0] Normal operation of the transmit buffer and its status bits.
[1] Flush the contents of the transmit buffer and update the
XMTSTAT
until this bit is cleared. During an active transmit the transmit buf-
fer in this state responds as if the transmit buffer is empty.

TWI FIFO Status Register (TWI_FIFO_STAT)

TWI FIFO Status Register (TWI_FIFO_STAT)
All bits are RO.
15 14 13 12 11 10
0 0 0 0 0
RCVSTAT[1:0] (Receive FIFO Status)
Figure 16-23. TWI FIFO Status Register

TWI FIFO Status

The fields in the
buffers' receive and transmit contents. The FIFO buffers do not discrimi-
nate between master data and slave data. By using the status and control
bits provided, the FIFO can be managed to allow simultaneous master and
slave operation.
16-40
XMTFLUSH
status bit to indicate the buffer is empty. This state is held
9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
register indicate the state of the FIFO
TWI_FIFO_STAT
ADSP-BF50x Blackfin Processor Hardware Reference
)
2 1 0
Reset = 0x0000
0 0 0
XMTSTAT[1:0] (Transmit
FIFO Status)