Timed Direction Mode; Functional Description; Input Noise Filtering (Debouncing) - Analog Devices ADSP-BF506F Hardware Reference Manual

bit in the
CDGINV
will decrement the counter. If this bit is set, a falling edge will decrement
the counter.

Timed Direction Mode

In this mode, the counter is incremented or decremented at each
cycle.
The state of the
decrements. The polarity can be selected by the
register. If this bit is cleared, a high
CNT_CONFIG
the counter, a low input will decrement it. If this bit is set, the polarity is
inverted.
The pin can be used to gate the clock. The polarity can be selected by
CDG
the bit in the
CDGINV
input will enable the counter, a low input will stop it. If this bit is set, the
polarity is inverted.

Functional Description

The following sections describe the various functions in more detail.

Input Noise Filtering (Debouncing)

In all modes, the three input pins can be filtered to present clean signals to
the GP counter logic. This filtering can be enabled or disabled by the
bit in the
CNT_CONFIG
for the pin.
CUD
ADSP-BF50x Blackfin Processor Hardware Reference
register. If this bit is cleared, a rising edge
CNT_CONFIG
input determines whether the counter increments or
CUD
register. If this bit is cleared, a high
CNT_CONFIG
register. Figure 13-2
General-Purpose Counter
bit in the
CUDINV
input will increment
CUD
shows the filtering operation
SCLK
CDG
DEBE
13-7