Sport Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers

The following sections describe the SPORT registers.
an overview of the available control registers.
Table 19-5. SPORT Register Mapping
Register Name
SPORT_TCR1
SPORT_TCR2
SPORT_TCLKDIV
SPORT_TFSDIV
SPORT_TX
SPORT_RCR1
SPORT_RCR2
SPORT_RCLK_DIV Receive clock
SPORT_RFSDIV
SPORT_RX
SPORT_STAT
SPORT_MCM1
ADSP-BF50x Blackfin Processor Hardware Reference
Function
Primary transmit
configuration register
Secondary transmit
configuration register
Transmit clock
divider register
Transmit frame sync divider register Ignored if external frame sync mode
Transmit data register
Primary receive
configuration register
Secondary receive
configuration register
divider register
Receive frame sync
divider register
Receive data register
Receive and transmit status
Primary multichannel mode
configuration register
SPORT Controller
Table 19-5
Notes
Bits [15:1] can only be written if
bit 0 = 0
Ignored if external SPORT clock
mode is selected
is selected
See description of FIFO buffering at
"SPORT Transmit Data
(SPORT_TX) Register" on
page 19-57
Bits [15:1] can only be written if
bit 0 = 0
Ignored if external SPORT clock
mode is selected
Ignored if external frame sync mode
is selected
See description of FIFO buffering at
"SPORT Receive Data
(SPORT_RX) Register" on
page 19-59
Configure this register before
enabling the SPORT
provides
19-45