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ADSP-BF59x Blackfin

Processor

Hardware Reference

Revision 1.0, May 2011

Part Number

82-100102-01

Analog Devices, Inc.

One Technology Way

a

Norwood, Mass. 02062-9106

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Summary of Contents for Analog Devices ADSP-BF59x Blackfin

Page 1: Hardware Reference
® ADSP-BF59x Blackfin Processor Hardware Reference Revision 1.0, May 2011 Part Number 82-100102-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2: Copyright Information
Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Registration for MyAnalog.com ..........xxxv EngineerZone ................ xxxv Social Networking Web Sites ..........xxxvi Supported Processors ..............xxxvi Product Information ..............xxxvii Analog Devices Web Site ............. xxxvii VisualDSP++ Online Documentation ........ xxxviii Technical Library CD ............xxxviii Notation Conventions ..............xxxix INTRODUCTION General Description of Processor ...........
Page 4 Active Mode (Moderate Power Savings) ......... 1-17 Sleep Mode (High Power Savings) ......... 1-17 Deep Sleep Mode (Maximum Power Savings) ......1-18 Hibernate State ..............1-18 Instruction Set Description ............1-18 Development Tools ..............1-19 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 5 Chip Bus Hierarchy Overview ............3-1 Interface Overview ................ 3-2 Internal Clocks ................ 3-3 Core Bus Overview ..............3-3 Peripheral Access Bus (PAB) ............. 3-4 PAB Arbitration ..............3-5 PAB Agents (Masters, Slaves) ..........3-5 PAB Performance ..............3-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 6 System Interrupt Status (SIC_ISR) Register ......4-12 System Interrupt Wakeup-Enable (SIC_IWR) Register ... 4-12 Programming Examples .............. 4-13 Clearing Interrupt Requests ........... 4-13 Unique Information for the ADSP-BF59x Processor ....4-15 Interfaces ................4-15 System Peripheral Interrupts ..........4-17 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 7 Descriptor List Mode ............5-14 Descriptor Array Mode ............. 5-15 Variable Descriptor Size ............ 5-15 Mixing Flow Modes ............5-16 Functional Description ............... 5-17 DMA Operation Flow ............5-17 DMA Startup ..............5-17 DMA Refresh ..............5-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 8 Memory DMA Priority and Scheduling ......5-46 Traffic Control ..............5-48 Programming Model ..............5-50 Synchronization of Software and DMA ........5-50 Single-Buffer DMA Transfers ..........5-52 Continuous Transfers Using Autobuffering ......5-53 Descriptor Structures ............5-55 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 9 DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT /MDMA_yy_CURR_X_COUNT) ......... 5-76 DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ... 5-77 DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ....5-78 DMA Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT) ........5-78 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 10 (HMDMAx_ECURGENT) ........... 5-87 Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) ......5-87 DMA Traffic Control Registers (DMA_TC_PER and DMA_TC_CNT) ......5-88 DMA_TC_PER Register ..........5-88 DMA_TC_CNT Register ..........5-88 Programming Examples .............. 5-90 viii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 11 Deep Sleep Mode ............... 6-9 Hibernate State ..............6-10 Operating Mode Transitions ..........6-10 Programming Operating Mode Transitions ......6-13 Dynamic Supply Voltage Control ........... 6-15 Power Supply Management ............ 6-15 Changing Voltage .............. 6-15 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 12 In Full-on Mode, Change VCO Frequency, Core Clock Frequency, and System Clock Frequency ......6-36 Changing Voltage Levels ............6-38 GENERAL-PURPOSE PORTS Overview ..................7-1 Features ..................7-1 Interface Overview ............... 7-2 External Interface ..............7-3 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 13 GPIO Set Registers (PORTxIO_SET) ........7-24 GPIO Clear Registers (PORTxIO_CLEAR) ......7-24 GPIO Toggle Registers (PORTxIO_TOGGLE) ...... 7-25 GPIO Polarity Registers (PORTxIO_POLAR) ....... 7-25 Interrupt Sensitivity Registers (PORTxIO_EDGE) ....7-26 GPIO Set on Both Edges Registers (PORTxIO_BOTH) ..7-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 14 Single Pulse Generation ............ 8-12 Pulse Width Modulation Waveform Generation ....8-13 PULSE_HI Toggle Mode ..........8-15 Externally Clocked PWM_OUT ........8-20 Using PWM_OUT Mode With the PPI ......8-21 Stopping the Timer in PWM_OUT Mode ......8-21 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 15 External Interface .............. 8-58 CORE TIMER Specific Information for the ADSP-BF59x ........9-1 Overview and Features ..............9-1 Timer Overview ................9-2 External Interfaces ..............9-2 Internal Interfaces ..............9-3 Description of Operation .............. 9-3 ADSP-BF59x Blackfin Processor Hardware Reference xiii...
Page 16 Watchdog Count (WDOG_CNT) Register ......10-5 Watchdog Status (WDOG_STAT) Register ......10-6 Watchdog Control (WDOG_CTL) Register ......10-7 Programming Examples .............. 10-8 Unique Information for the ADSP-BF59x Processor ....10-10 UART PORT CONTROLLERS Specific Information for the ADSP-BF59x ........11-1 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 17 UART Line Control (UART_LCR) Register ......11-21 UART Modem Control (UART_MCR) Register ....11-23 UART Line Status (UART_LSR) Register ......11-24 UART Transmit Holding (UART_THR) Register ....11-25 UART Receive Buffer (UART_RBR) Register ...... 11-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 18 Description of Operation ............12-6 TWI Transfer Protocols ............12-6 Clock Generation and Synchronization ......12-7 Bus Arbitration ..............12-8 Start and Stop Conditions ..........12-8 General Call Support ............12-9 Fast Mode ..............12-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 19 TWI Slave Mode Control Register (TWI_SLAVE_CTL) ..12-26 TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 12-28 TWI Slave Mode Status Register (TWI_SLAVE_STAT) ..12-28 TWI Master Mode Control Register (TWI_MASTER_CTL) ............ 12-29 TWI Master Mode Address Register (TWI_MASTER_ADDR) ..........12-32 ADSP-BF59x Blackfin Processor Hardware Reference xvii...
Page 20 Slave Mode Setup ..............12-50 Electrical Specifications ............12-56 Unique Information for the ADSP-BF59x Processor ....12-56 SPI-COMPATIBLE PORT CONTROLLER Specific Information for the ADSP-BF59x ........13-1 Overview ..................13-2 Features ..................13-2 Interface Overview ..............13-3 xviii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 21 Slave Mode Operation (Non-DMA) ........13-19 Slave Ready for a Transfer ............ 13-21 Programming Model ..............13-21 Beginning and Ending an SPI Transfer ......... 13-21 Master Mode DMA Operation ..........13-23 Slave Mode DMA Operation ..........13-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 22 Stopping ................ 13-46 DMA-Based Transfer ............13-47 DMA Initialization Sequence .......... 13-47 SPI Initialization Sequence ..........13-48 Starting a Transfer ............13-49 Stopping a Transfer ............13-50 Unique Information for the ADSP-BF59x Processor ....13-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 23 Channel Selection Register ..........14-22 Multichannel DMA Data Packing ........14-23 Support for H.100 Standard Protocol ........14-24 2× Clock Recovery Control ..........14-24 Functional Description ............. 14-25 Clock and Frame Sync Frequencies ........14-25 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 24 SPORT Registers ..............14-44 Register Writes and Effective Latency ........14-45 SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers ....14-46 SPORT Receive Configuration (SPORT_RCR1 and SPORT_RCR2) Registers ....14-51 Data Word Formats ............. 14-55 xxii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 25 Clock Gating Functionality ..........14-74 Modes of Operation ............14-75 Gated Clock Mode 0 – SPORT Gated Clocks Without Using TIMERs ............. 14-75 Gated Clock Mode 1 – SPORT Gated Clocks Using TIMERs ..............14-75 ADSP-BF59x Blackfin Processor Hardware Reference xxiii...
Page 26 1, 2, or 3 External Frame Syncs ........15-15 2 or 3 Internal Frame Syncs ........15-16 Data Output (TX) Modes ..........15-16 No Frame Syncs ............15-17 1 or 2 External Frame Syncs ........15-17 xxiv ADSP-BF59x Blackfin Processor Hardware Reference...
Page 27 Reset and Power-up ..............16-3 Hardware Reset ..............16-4 Software Resets ..............16-5 Reset Vector ................16-6 Servicing Reset Interrupts ............16-6 Basic Booting Process ..............16-8 Block Headers ..............16-10 Block Code ..............16-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 28 CRC Checksum Calculation ..........16-30 Load Functions ..............16-30 Calling the Boot Kernel at Runtime ........16-32 Debugging the Boot Process ..........16-32 Boot Management ..............16-35 Booting a Different Application .......... 16-35 Multi-DXE Boot Streams ..........16-36 xxvi ADSP-BF59x Blackfin Processor Hardware Reference...
Page 29 Zero Word (BK_ZEROS) ............ 16-57 Ones Word (BK_ONES) ............. 16-58 Data Structures ................. 16-58 ADI_BOOT_HEADER ............16-59 ADI_BOOT_BUFFER ............16-59 ADI_BOOT_DATA ............16-59 dFlags Word ..............16-63 Callable ROM Functions for Booting ........16-64 BFROM_FINALINIT ............16-64 ADSP-BF59x Blackfin Processor Hardware Reference xxvii...
Page 30 Managing Core and System Clocks ........17-2 Configuring and Servicing Interrupts .......... 17-2 Data Delays, Latencies and Throughput ........17-2 Bus Priorities ................17-3 High-Frequency Design Considerations ........17-3 Signal Integrity ..............17-3 Decoupling Capacitors and Ground Planes ......17-4 xxviii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 31 Dynamic Power Management Registers ........A-11 PPI Registers ................A-12 SPI Controller Registers ............. A-12 SPORT Controller Registers ............A-14 SPORT Clock Gating Register ........... A-17 UART Controller Registers ............A-18 TWI Registers ................A-19 ADSP-BF59x Blackfin Processor Hardware Reference xxix...
Page 32 Boundary-Scan Architecture ............B-2 Instruction Register ..............B-4 Public Instructions ..............B-5 EXTEST – Binary Code 00000 ........... B-6 SAMPLE/PRELOAD – Binary Code 10000 ....... B-6 BYPASS – Binary Code 11111 ..........B-6 Boundary-Scan Register ............B-7 INDEX ADSP-BF59x Blackfin Processor Hardware Reference...
Page 33: Preface
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruc- tion set. Programmers who are unfamiliar with Analog Devices processors...
Page 34: Manual Contents
• Chapter 7, “General-Purpose Ports” Describes the general-purpose I/O ports, including the structure of each port, multiplexing, configuring the pins, and generating interrupts. • Chapter 8, “General-Purpose Timers” Describes the eight general-purpose timers. xxxii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 35 16 bits of data and is used for digital video and data converter applications. • Chapter 16, “System Reset and Booting” Describes the booting methods, booting process and specific boot modes for the processor. ADSP-BF59x Blackfin Processor Hardware Reference xxxiii...
Page 36: What's New In This Manual
This hardware reference is a companion document to the Blackfin Processor Programming Reference. What’s New in This Manual This revision (1.0) is the second release of the ADSP-BF59x Blackfin Pro- cessor Hardware Reference. Minor typographical errors have been corrected in this revision.
Page 37: Registration For Myanalog.com
P.O. Box 9106 Norwood, MA 02062-9106 Registration for MyAnalog.com is a free feature of the Analog Devices Web site that allows MyAnalog.com customization of a Web page to display only the latest information about products you are interested in. Click Register to use this site...
Page 38: Social Networking Web Sites
• LinkedIn: Network with the LinkedIn group, Analog Devices SHARC: http://www.linkedin.com Supported Processors The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®. Blackfin (ADSP-BFxxx) Processors The name Blackfin refers to a family of 16-bit, embedded processors.
Page 39: Product Information
VisualDSP++ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, ADSP-2136x, and ADSP-214xx. Product Information Product information can be obtained from the Analog Devices Web site, VisualDSP++ online Help system, and a technical library CD. Analog Devices Web Site The Analog Devices Web site, , provides information www.analog.com...
Page 40: Visualdsp++ Online Documentation
ADSP-218x, and ADSP-219x. To order the technical library CD, go to http://www.analog.com/proces- , navigate to the manuals page for your processor, click the sors/manuals request CD check mark, and fill out the order form. xxxviii ADSP-BF59x Blackfin Processor Hardware Reference...
Page 41: Notation Conventions
Preface Data sheets, which can be downloaded from the Analog Devices Web site, change rapidly, and therefore are not included on the technical library CD. Technical manuals change periodically. Check the Web site for the latest manual revisions and associated documentation errata.
Page 42 A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 43: Introduction
® The ADSP-BF59x processor is a member of the Blackfin family of prod- ucts, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like micro- processor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
Page 44: Portable Low-Power Architecture
This capability can result in a substantial reduction in power consumption, compared with just ADSP-BF59x Blackfin Processor Hardware Reference...
Page 45: Peripherals
• Two dual-channel, full-duplex synchronous Serial Ports (SPORTs), supporting eight stereo I S channels • One UART with IrDA® support These peripherals are connected to the core via several high bandwidth buses, as shown in Figure 1-1. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 46: Memory Architecture
I/O control registers, occupy sep- arate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low latency on-chip memory, ADSP-BF59x Blackfin Processor Hardware Reference...
Page 47: Internal Memory
Blackfin processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Control registers for on-chip I/O devices are mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated ADSP-BF59x Blackfin Processor Hardware Reference...
Page 48: Dma Support
Examples of DMA types supported include: • A single, linear buffer that stops upon completion • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ADSP-BF59x Blackfin Processor Hardware Reference...
Page 49: General-Purpose I/O (Gpio)
Reading the GPIO status register allows software to interrogate the sense of the pins. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 50: Two-Wire Interface
C bus protocol. The Philips I C Bus Specification version 2.1 covers many variants of I C. The TWI controller includes these features: • Simultaneous master and slave operation on multiple device systems • Support for multi-master data arbitration ADSP-BF59x Blackfin Processor Hardware Reference...
Page 51: Parallel Peripheral Interface
The input clock supports parallel data rates up to half the system clock rate. In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or 10-bit data elements. On-chip decode of embedded preamble control and synchronization information is supported. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 52 PPI_CLK • Data receive with internally generated frame syncs • Data receive with externally generated frame syncs • Data transmit with internally generated frame syncs • Data transmit with externally generated frame syncs 1-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 53: Sport Controllers
• Word length Each SPORT supports serial data words from 3 to 32 bits in length, transferred in most significant bit first or least significant bit first format. ADSP-BF59x Blackfin Processor Hardware Reference 1-11...
Page 54 DMA. • Multichannel capability Each SPORT supports 128 channels out of a 1024-channel win- dow and is compatible with the H.100, H.110, MVIP-90, and HMVIP standards. 1-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 55: Serial Peripheral Interface (Spi) Ports
TMRCLK PPI_CLK SCLK The timer units can be used in conjunction with the UARTs to measure the width of the pulses in the datastream to provide an autobaud detect function for a serial channel. ADSP-BF59x Blackfin Processor Hardware Reference 1-13...
Page 56: Uart Port
The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA chan- nels have lower priority than most DMA channels because of their relatively low service rates. 1-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 57: Watchdog Timer
If configured to generate a hardware reset, the watchdog timer resets both the CPU and the peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the watchdog control register. ADSP-BF59x Blackfin Processor Hardware Reference 1-15...
Page 58: Clock Signals
In addition, dynamic power management provides the control functions to dynamically alter the processor core supply volt- age to further reduce power dissipation. Control of clocking to each of the peripherals also reduces power consumption. 1-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 59: Full-On Mode (Maximum Performance)
). If bypass is disabled, the processor transitions to the PLL_CTL full on mode. If bypass is enabled, the processor transitions to the active mode. When in the sleep mode, system DMA access to L1 memory is not supported. ADSP-BF59x Blackfin Processor Hardware Reference 1-17...
Page 60: Deep Sleep Mode (Maximum Power Savings)
C and C++ source code. In addition, the architecture supports both user (algorithm/application code) and supervisor (O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core resources. 1-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 61: Development Tools
® emulators and the VisualDSP++ development environment. The same emulator hardware that supports other Analog Devices products also fully emulates the Blackfin processor family. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an...
Page 62 Visu- alDSP++ editor. These capabilities permit programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s com- mand-line switches 1-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 63 VDK-based objects, and visualizing the system state during application debug. Analog Devices emulators use the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspec- tion and modification of memory, registers, and processor stacks.
Page 64 Development Tools 1-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 65: Memory
The upper portion of internal memory space is allocated to the core and system MMRs. Accesses to this area are allowed only when the processor is in supervisor or emulation mode (see the Operating Modes and States chapter of the Blackfin Processor Programming Reference). ADSP-BF59x Blackfin Processor Hardware Reference...
Page 66: L1 Instruction Sram
L1 instruction SRAM subbanks. Table 2-1. L1 Instruction Memory Subbanks Memory Bbank Memory Subbank Memory Start Location for ADSP-BF59x Processors Instruction Bank A 0xFFA0 0000 Instruction Bank A 0xFFA0 1000 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 67: L1 Instruction Rom
Table 2-2. L1 Data Memory SRAM Subbank Start Addresses Memory Bank and Subbank ADSP-BF59x Processors Data Bank A, Subbank 0 0xFF80 0000 Data Bank A, Subbank 1 0xFF80 1000 Data Bank A, Subbank 2 0xFF80 2000 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 68: Boot Rom
The complete set of memory-related MMRs is described in the Blackfin Processor Programming Reference. Several MMRs have bit definitions spe- cific to the processors described in this manual. These registers are described in the following sections. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 69: Dtest_Command Register
L1 Inst SRAM from 0xFFA0 4000 to 0xFFA0 7FFF 15 14 13 12 11 10 Read/Write Access ADR[15:14] 0 - Read access Address bits [15:14] 1 - Write access ADR[10:3] Reserved - Write 1 Address bits [10:3] Figure 2-2. Data Test Command Register ADSP-BF59x Blackfin Processor Hardware Reference...
Page 70: Itest_Command Register
This register may be used to gain access to the 16K bytese of L1 instruc- tion SRAM from address 0xFFA04000 to address 0xFFA07FFF. All other regions of L1 memory—both data and instruction—are accessed using the register. DTEST_COMMAND ADSP-BF59x Blackfin Processor Hardware Reference...
Page 71: Dmem_Control Register
Reset = 0x00000001 15 14 13 12 11 10 ENICPLB (Instruction Cache- ability Protection Lookaside Buffer Enable) 0 - CPLBs disabled. Minimal address checking only 1 - CPLBs enabled Figure 2-5. Instruction Memory Control Register ADSP-BF59x Blackfin Processor Hardware Reference...
Page 72: Dcplb_Datax Registers
User Mode (writes generate in User Mode (reads generate protection violation exceptions) protection violation exceptionss) 1 - Write access permitted 1 - Read access permitted in User Mode in User Mode Figure 2-6. Data CPLB Data Register ADSP-BF59x Blackfin Processor Hardware Reference...
Page 73: Icplb_Datax Registers
1 - Valid (enabled) CPLB entry protection violation exceptionss) 1 - Read access permitted CPLB_LOCK in User Mode 0 - Unlocked, CPLB entry replaceable 1 - Locked, CPLB entry not replaceable Figure 2-7. Instruction CPLB Data Register ADSP-BF59x Blackfin Processor Hardware Reference...
Page 74 Processor-Specific MMRs 2-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 75: Chip Bus Hierarchy
“Interface Overview” on page 3-2 Chip Bus Hierarchy Overview ADSP-BF59x Blackfin processors feature a powerful chip bus hierarchy on which all data movement between the processor core, internal memory, and its rich set of peripherals occurs. The chip bus hierarchy includes the controllers for system interrupts, test/emulation, and clock and power management.
Page 76: Interface Overview
INSTRUCTION PROCESSOR SRAM & LOAD DATA CORE CLOCK LOAD DATA (CCLK) DOMAIN STORE DATA SYSTEM CLOCK (SCLK) DOMAIN CORE (DCB) CONTROLLER EXT. PERIPHERAL (DEB) ACCESS BUS (PAB) BOOT ACCESS (DAB) Figure 3-1. Processor Bus Hierarchy ADSP-BF59x Blackfin Processor Hardware Reference...
Page 77: Internal Clocks
64 bits. When the instruction request is filled, the 64-bit read can contain a single 64-bit instruction or any combination of 16-, 32-, or 64-bit (partial) instructions. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 78: Peripheral Access Bus (Pab)
All peripheral resources accessed through the PAB are mapped into the system MMR space of the processor memory map. The core accesses system MMR space through the PAB bus. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 79: Pab Arbitration
The slaves on the PAB bus are: • System event controller • Clock and power management controller • Watchdog timer • Timer 0–2 • SPORT0–1 • SPI0–1 • General-purpose ports • UART • PPI • TWI • DMA controller ADSP-BF59x Blackfin Processor Hardware Reference...
Page 80: Pab Performance
SRAM. The processor has a programmable priority arbitration policy on the DAB. Table 3-1 shows the default arbitration priority. Table 3-1. DAB and DCB Arbitration Priority DAB, DCB Master Default Arbitration Priority PPI receive or transmit 0 - highest SPORT0 receive ADSP-BF59x Blackfin Processor Hardware Reference...
Page 81: Dab Bus Agents (Masters)
When two or more DMA master channels are actively requesting the DAB, bus utilization is considerably higher due to the DAB’s pipelined design. Bus arbitration cycles are concurrent with the previous DMA access’s data cycles. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 82: Dab And Dcb Performance
DMA controllers cannot perform locked transfers. DMA access to L1 memory can only be stalled by an access already in progress from another DMA channel. Latencies caused by these stalls are in addition to any arbitration latencies. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 83: System Interrupts
“Unique Information for the ADSP-BF59x Processor” on page 4-15. Overview The processor system has numerous peripherals, which therefore require many supporting interrupts. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 84: Features
This mapping is programmable, and individual interrupt sources can be masked in the SIC. The CEC of the processor manages five types of activities or events: • Emulation • Reset • Nonmaskable interrupts (NMI) ADSP-BF59x Blackfin Processor Hardware Reference...
Page 85 IVG7 IVG13 peripheral purposes. Refer to Table 4-1. Table 4-1. System and Core Event Mapping Event Source Core Event Name Core events Emulation (highest priority) Reset Exception Reserved – Hardware error IVHW Core timer IVTMR ADSP-BF59x Blackfin Processor Hardware Reference...
Page 86: System Peripheral Interrupts
 For general-purpose interrupts with multiple peripheral interrupts assigned to them, take special care to ensure that software correctly processes all pending interrupts sharing that input. Software is responsible for prioritizing the shared interrupts. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 87 SIC_ISR the peripherals sharing the input has asserted its interrupt output. The ser- vice routine should fully process all pending, shared interrupts before executing the RTI, which enables further interrupt generation on that interrupt input. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 88 Dynamic Power Manage- ment chapter. register has no effect unless the core is idled. By default, all SIC_IWR interrupts generate a wakeup request to the core. However, for some ADSP-BF59x Blackfin Processor Hardware Reference...
Page 89: Programming Model
If the default peripheral-to-IVG assignments shown in Table 4-1 on page 4-3 Table 4-2 on page 4-11 are acceptable, then interrupt initial- ization involves only: • Initialization of the core event vector table (EVT) vector address entries ADSP-BF59x Blackfin Processor Hardware Reference...
Page 90: System Interrupt Processing Summary
A is not masked, the process IVGx proceeds to Step 7. 7. The event vector table (EVT) is accessed to look up the appropriate vector for interrupt A’s interrupt service routine (ISR). ADSP-BF59x Blackfin Processor Hardware Reference...
Page 91 It should be noted that emulation, reset, NMI, and exception events, as well as hardware error ( ) and core timer ( ) interrupt requests, IVHW IVTMR enter the interrupt processing chain at the level and are not affected ILAT ADSP-BF59x Blackfin Processor Hardware Reference...
Page 92: System Interrupt Controller Registers
4-bit field within in order to configure a peripheral interrupt ID for a SIC_IAR particular IVG priority. Refer to Table 4-1 on page 4-3 for information on SIC_IAR mappings for this specific processor. 4-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 93 ID Grouping 3 ID Grouping 1 ID Grouping 2 Figure 4-2. System Interrupt Assignment Register Table 4-2. IVG Select Definitions General-purpose Interrupt Value in SIC_IAR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15 ADSP-BF59x Blackfin Processor Hardware Reference 4-11...
Page 94: System Interrupt Mask (Sic_Imask) Register
A "1" indicates that it is configured to do so. Refer to Table 4-1 on page 4-3 Table 4-2 on page 4-11 for informa- tion on how peripheral interrupt IDs are mapped to the SIC_IWR register(s) for this particular processor. 4-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 95: Programming Examples
GPIOs, and error requests require explicit acknowledge instruc- tions, which are typically performed by efficient W1C (write-1-to-clear) operations. Listing 4-1 shows a representative example of how a GPIO interrupt request might be serviced. ADSP-BF59x Blackfin Processor Hardware Reference 4-13...
Page 96 In service routines consisting of a few CCLK SCLK instructions only, two instructions are recommended between the SSYNC clear command and the RTI instruction. However, one instruction SSYNC is typically sufficient if the clear command performs in the very beginning 4-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 97: Unique Information For The Adsp-Bf59X Processor
SIC. It also shows how the eight SIC_IAR registers control the assignment to the nine available peripheral request inputs of the CEC.  The memory-mapped , and registers are part of ILAT IMASK IPEND the CEC controller. ADSP-BF59x Blackfin Processor Hardware Reference 4-15...
Page 98 GP TIMER 2 PORT G INTERRUPT A PORT G INTERRUPT B RESERVED RESERVED RESERVED RESERVED DMA 12/13 (MEM DMA STREAM 0) DMA 14/15 (MEM DMA STREAM 1) WATCHDOG TIMER Figure 4-3. Interrupt Routing Overview 4-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 99: System Peripheral Interrupts
Reserved IVG7 Bit 25 SIC_IAR3[7:4] Reserved IVG7 Bit 24 SIC_IAR3[3:0] IVG12 Bit 23 SIC_IAR2[31:28] Port G Interupt B IVG12 Bit 22 SIC_IAR2[27:24] Port G Interrupt A IVG12 Bit 21 SIC_IAR2[23:20] GP Timer 2 IVG11 ADSP-BF59x Blackfin Processor Hardware Reference 4-17...
Page 100 SPI0 Status IVG7 Bit 4 SIC_IAR0[19:16] SPORT1 Status IVG7 Bit 3 SIC_IAR0[15:12] SPORT0 Status IVG7 Bit 2 SIC_IAR0[11:8] PPI Status IVG7 Bit 1 SIC_IAR0[7:4] DMA Error (generic) IVG7 Bit 0 SIC_IAR0[3:0] PLL Wakeup IVG7 4-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 101: Direct Memory Access
To determine how each of the DMAs is multiplexed with other functional pins, refer to Table 7-1 on page 7-3 through Table 7-2 on page 7-4 Chapter 7, “General-Purpose Ports”. For a list of MMR addresses for each DMA, refer to Chapter A, “System Assignments”. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 102: Overview And Features
5-101 to determine whether it applies to this product. All DMAs can transport data to and from on-chip and off-chip memories, including L1 and SDRAM. The L1 scratchpad memory cannot be accessed by DMA. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 103 3-word descriptors, each containing a link pointer and a 32-bit address • 1-D DMA, using a linked list of 5-word descriptors containing a link pointer, a 32-bit address, the buffer length, and a configuration ADSP-BF59x Blackfin Processor Hardware Reference...
Page 104: Dma Controller Overview
Blackfin processor memory. Internal Interfaces Figure 3-1 on page 3-2 shows the dedicated DMA buses used by the DMA controller to interconnect L1 memory, the on-chip peripherals, and the EBIU port. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 105: Peripheral Dma
DMA channels and peripherals. The default DMA channel priority and mapping, shown in Table 5-9 on page 5-103, can be changed by altering the 4-bit field in the regis- PMAP DMAx_PERIPHERAL_MAP ters for the peripheral DMA channels. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 106: Memory Dma
These include L1 memory and external synchronous/asynchronous memories. Each MDMA channel contains a DMA FIFO, an 8-word by 16-bit FIFO block used to transfer data to and from either L1 or the DCB and DEB ADSP-BF59x Blackfin Processor Hardware Reference...
Page 107 Both ends of the MDMA FIFO for a given stream are granted priority at the same time. Each pair shares an 8-word deep 16-bit FIFO. The source DMA engine fills the FIFO, while the ADSP-BF59x Blackfin Processor Hardware Reference...
Page 108: Handshaked Memory Dma (Hmdma) Mode
MDMA stalls again and waits for the next trigger. Handshake operation is not only useful for controlling the timing of memory-to-memory transfers, it also enables the MDMA to operate with ADSP-BF59x Blackfin Processor Hardware Reference...
Page 109: Modes Of Operation
For basic operation, the software performs these steps: • Write the source or destination address to the 32-bit register. DMAx_START_ADDR • Write the number of data words to be transferred to the 16-bit register. DMAx_X_COUNT ADSP-BF59x Blackfin Processor Hardware Reference...
Page 110 DMA_DONE DMA_ERR whether the DMA is currently running ( bit). The DMA_RUN DMA_DONE bits also function as interrupt latch bits. They must be cleared DMA_ERR by write-one-to-clear (W1C) operations by the interrupt service routine. 5-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 111: Stop Mode
64K × 64K elements, as well as arbitrary DMAx_X_MODIFY values up to ±32K bytes. Furthermore, DMAx_Y_MODIFY DMAx_Y_MODIFY be negative, allowing implementation of interleaved datastreams. The values specify the row and column sizes, DMAx_X_COUNT DMAx_Y_COUNT where must be 2 or greater. DMAx_X_COUNT ADSP-BF59x Blackfin Processor Hardware Reference 5-11...
Page 112: Examples Of Two-Dimensional Dma
Examples of Two-Dimensional DMA Example 1: Retrieve a 16 × 8 block of bytes from a video frame buffer of size (N × M) pixels: DMAx_X_MODIFY = 1 DMAx_X_COUNT = 16 5-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 113: Descriptor-Based Dma Operation
DMA controller loads the descriptor from memory and over- writes the affected DMA registers by its own control. Descriptors can be fetched from L1 memory using the DCB bus or from external memory using the DEB bus. ADSP-BF59x Blackfin Processor Hardware Reference 5-13...
Page 114: Descriptor List Mode
DCB and DEB buses. In small descriptor mode this pointer is just 16 bits wide. For this reason, the next descriptor must reside in the same 64K byte address space 5-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 115: Descriptor Array Mode
DMA is in two-dimensional mode, but the YCNT YMOD values do not need to change. All the other registers not loaded from the descriptor retain their prior val- ues, although the , and DMAx_CURR_ADDR DMAx_CURR_X_COUNT ADSP-BF59x Blackfin Processor Hardware Reference 5-15...
Page 116: Mixing Flow Modes
FLOW NDSIZE fields can also be altered. A small descriptor might be used to loop back to the first descriptor if a descriptor array is used in an endless manner. If the 5-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 117: Functional Description
NDSIZE FLOW DMAx_CONFIG any, are fetched from descriptor elements in memory. After the descriptor fetch, if any, is completed, DMA operation begins, initiated by writing with = 1. DMAx_CONFIG DMAEN ADSP-BF59x Blackfin Processor Hardware Reference 5-17...
Page 118 INTO TEMPORARY DESCRIPTOR FETCH COUNTERS FLOW = 4 TEST FLOW FLOW = 6 OR 7 COPY NEXT DESCRIPTOR POINTER TO CURRENT DESCRIPTOR POINTER Figure 5-1. DMA Flow, From DMA Controller’s Point of View (1 of 2) 5-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 119 IF FLOW = 4, MAX_SIZE = 7 CLEAR DMA_RUN IN IF FLOW = 6, MAX_SIZE = 8 IRQ_STATUS. IF FLOW = 7, MAX_SIZE = 9 Figure 5-2. DMA Flow, From DMA Controller’s Point of View (2 of 2) ADSP-BF59x Blackfin Processor Hardware Reference 5-19...
Page 120 (that is, in descriptor NDPH NDPL array mode, = 4), then the transfer from into FLOW NDPH NDPL does not occur. Instead, descriptor fetch indexing DMAx_CURR_DESC_PTR begins with the value in DMAx_CURR_DESC_PTR 5-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 121 • is copied to DMAx_START_ADDR DMAx_CURR_ADDR • is copied to DMAx_X_COUNT DMAx_CURR_X_COUNT • is copied to DMAx_Y_COUNT DMAx_CURR_Y_COUNT ADSP-BF59x Blackfin Processor Hardware Reference 5-21...
Page 122: Dma Refresh
= 6 (small descriptor list) the DMA controller copies the FLOW 32-bit into . Next, the DMAx_NEXT_DESC_PTR DMAx_CURR_DESC_PTR DMA controller fetches a descriptor from memory into the DMA 5-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 123 FLOW next work unit for that channel, which must contend with other channels for priority on the memory buses. On the first memory transfer of the new work unit, the DMA controller updates the ADSP-BF59x Blackfin Processor Hardware Reference 5-23...
Page 124: Work Unit Transitions
SYNC descriptor prior to the transition controls the transition behavior. In contrast, in receive channels, the bit of the first descriptor SYNC of the next descriptor chain controls the transition. 5-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 125: Dma Transmit And Mdma Source
= 0 selects continuous transition on a work unit in = 0 mode SYNC FLOW with interrupt enabled. The interrupt service routine may begin execution while the final data is still draining from the FIFO to the peripheral. This ADSP-BF59x Blackfin Processor Hardware Reference 5-25...
Page 126: Dma Receive
0 in the new work unit’s value, a continuous SYNC DMAx_CONFIG transition is selected. In this mode, any data items received into the DMA FIFO while the channel was paused are retained, and they are the first 5-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 127 = 4, 6, or 7, then the FLOW next descriptor must have the same word size. For any DMA receive (memory write) channel, there is no restriction on changes of memory space (internal vs. external) between descriptors or ADSP-BF59x Blackfin Processor Hardware Reference 5-27...
Page 128: Stopping Dma Transfers
The DMA controller flags conditions that cause the DMA process to end abnormally (abort). This functionality is provided as a tool for system development and debug to detect DMA-related programming errors. DMA errors (aborts) are detected by the DMA channel module in the 5-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 129 . See Table 5-2 on NDSIZE FLOW page 5-31. • A disallowed register write occurred while the channel was run- ning. Only the registers can be DMAx_CONFIG DMAx_IRQ_STATUS written when = 1. DMA_RUN ADSP-BF59x Blackfin Processor Hardware Reference 5-29...
Page 130 MDMA DMAx_CONFIG stream are not equal. • Descriptor chain indicates data buffers that are not in the same internal/external memory space. • In 2-D DMA, X_COUNT 5-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 131: Dma Control Commands
DMA transfers which that peripheral can support. It is important that application software be written to comply with certain restrictions regard- ing work units and descriptor chains (described later in this section) so that the peripheral operates properly whenever it issues DMA control commands. ADSP-BF59x Blackfin Processor Hardware Reference 5-31...
Page 132 During this period of time, the channel does not grant DMA requests. Once all pending reads have been flushed from the chan- nel’s pipelines, the channel resets its counters and FIFO and starts prefetch reads from memory. DMA data requests from the 5-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 133 If a channel programmed for receive (memory write) receives a command, the channel stops granting new DMA requests Finish while it drains its FIFO. Any DMA data received by the DMA con- troller prior to the command is written to memory. When Finish ADSP-BF59x Blackfin Processor Hardware Reference 5-33...
Page 134: Restrictions
If the value of the current work DMAx_CURR_X_COUNT DMAx_CURR_Y_COUNT unit is sufficiently large that it is always at least five more than the 5-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 135: Receive Restart Or Finish
This requires, how- ever, that the user programs the descriptors for all work units managed by ADSP-BF59x Blackfin Processor Hardware Reference 5-35...
Page 136: Handshaked Memory Dma Operation
Once the transfer has been requested, no further handshake can hold off the DMA from transferring the entire block, except by 5-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 137: Pipelining Dma Requests
16-bit twos-complement data representation: if they return zero, all requested block transfers have been performed. A positive value signals up to 32767 requests that haven’t been served yet and indicates that the MDMA is currently processing. Negative values indicate the number of ADSP-BF59x Blackfin Processor Hardware Reference 5-37...
Page 138 In the receive example shown in Figure 5-4, the Blackfin processor again does not use the FIFO’s internal control mechanism. Rather than testing the empty flag, the processor counts the number of data words available in 5-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 139: Hmdma Interrupts
HMDMAx_ECOUNT register. HMDMAx_ECURGENT HMDMA Interrupts In addition to the normal MDMA interrupt channels, the handshake hardware provides two new interrupt sources for each input. The DMARx ADSP-BF59x Blackfin Processor Hardware Reference 5-39...
Page 140: Dma Performance
DMA transfer often depends on applica- tion-level circumstances. For best performance consider the following system software architecture questions. • What is the required DMA bandwidth? • Which DMA transfers have real-time requirements and which do not? 5-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 141: Dma Throughput
DCB bus, which runs at the rate. CCLK Each memory DMA channel has a maximum transfer rate of one 16-bit word per system clock ( ) cycle. SCLK ADSP-BF59x Blackfin Processor Hardware Reference 5-41...
Page 142 • Reads from DMA registers other than control/status registers use one PAB bus wait state, delaying the core for several core clocks. 5-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 143 FIFO, and then automatically turns around and delivers all available data from the FIFO to the destination buffer. The burst length is dependent on traffic, and is equal to three plus the memory latency at the ADSP-BF59x Blackfin Processor Hardware Reference 5-43...
Page 144: Memory Dma Timing Details
Typically, DMA transfers for a given peripheral occur at regular intervals. Generally, the shorter the interval, the higher the priority that should be assigned to the peripheral. If the average bandwidth of all the peripherals 5-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 145 DMARx register. If handshaked operation is disabled, soft- HMDMAx_ECURGENT ware can control urgency of requests directly by altering the bit field in the register. HMDMAx_CONTROL ADSP-BF59x Blackfin Processor Hardware Reference 5-45...
Page 146: Memory Dma Priority And Scheduling
If two MDMA streams are used (S0-D0 and S1-D1), the user may choose to allocate bandwidth either by fixed stream priority or by a round-robin scheme. This is selected by programming the MDMA_ROUND_ROBIN_PERIOD field in the register (see “Static Channel Prioritization” on DMA_TC_PER page 5-44). 5-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 147 P from . In this cycle, if the other MDMA_ROUND_ROBIN_PERIOD MDMA stream is ready to perform a transfer, the stream selection is locked on the new MDMA stream. If the other MDMA stream is not ADSP-BF59x Blackfin Processor Hardware Reference 5-47...
Page 148: Traffic Control
Traffic control is an important consideration in optimizing use of DMA resources. Traffic control is a way to influence how often the transfer direction on the data buses may change, by automatically grouping same direction transfers together. The DMA block provides a traffic control 5-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 149 90%. To disable preferential DMA prioritization, program the reg- DMA_TC_PER ister to 0x0000. ADSP-BF59x Blackfin Processor Hardware Reference 5-49...
Page 150: Programming Model
(for example, at the end of a descriptor list), or that interrupts are spaced sufficiently far apart in time that system processing budgets can guarantee every interrupt is serviced. Note, since every interrupt channel 5-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 151 DMA register update is visible to an MMR read to the point where DMA and core accesses to memory become strictly ordered. If the DMA FIFO ADSP-BF59x Blackfin Processor Hardware Reference 5-51...
Page 152: Single-Buffer Dma Transfers
The user may choose to use a sin- gle descriptor in memory, in which case the software only needs to write and the registers. Alternatively, the DMAx_CONFIG DMAx_NEXT_DESC_PTR 5-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 153: Continuous Transfers Using Autobuffering
DMA inner loop. In this way, a traditional double buffer or “ping-pong” scheme can be implemented. For example, two 512-word sub-buffers inside a 1K-word buffer could be used to receive 16-bit peripheral data with the settings in Table 5-4. ADSP-BF59x Blackfin Processor Hardware Reference 5-53...
Page 154 4 same as DMAx_X_MODIFY for contiguous sub-buffers • The synchronization core might read to determine DMAx_Y_COUNT which sub-buffer is currently being transferred, and then allow one full sub-buffer to account for pipelining. For example, if a read of 5-54 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 155: Descriptor Structures
DMA DMAx_CONFIG descriptors. In particular: • The lower byte of specifies the DMA transfer to be DMAx_CONFIG performed by the current descriptor (for example 2-D inter- rupt-enable mode) ADSP-BF59x Blackfin Processor Hardware Reference 5-55...
Page 156: Descriptor Queue Management
The recommended method for synchronization of a descriptor queue is through the use of an interrupt. The descriptor queue is structured so that at least the final valid descriptor is always programmed to generate an interrupt. 5-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 157: Descriptor Queue Using Interrupts On Every Descriptor
DMA channel, provided the rest of the descriptor data structure is initialized in advance. It is necessary, however, to synchronize the soft- ware to the DMA to correctly determine whether the new or the old value was read by the DMA channel. DMAx_CONFIG ADSP-BF59x Blackfin Processor Hardware Reference 5-57...
Page 158: Descriptor Queue Using Minimal Interrupts
DMA unit. In values ≥ 4 and other words, all but the last active descriptors contain FLOW 5-58 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 159 (for example zero) back to the non-interrupt software indicating that the queue has stopped. This simple handler should be able to be coded in a very small number of instructions. ADSP-BF59x Blackfin Processor Hardware Reference 5-59...
Page 160: Software Triggered Descriptor Fetches
0x4, 0x6, or 0x7. In this mode of oper- FLOW ation, the field should at least span up to the field to NDSIZE DMACFG overwrite the configuration register immediately. 5-60 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 161 A single MMR write is required to trigger the next DMA sequence. Especially when applied to MDMA channels, such scenarios play an important role. Usually, the timing of MDMAs cannot be controlled (see ADSP-BF59x Blackfin Processor Hardware Reference 5-61...
Page 162: Dma Registers
DMA. All channels have an identical set of registers as summarized in Table 5-6. Table 5-6 lists the generic names of the DMA registers. For each register, the table also shows the MMR offset, a brief description of the register, 5-62 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 163 0x20 Current descriptor pointer Current CURR_DESC_PTR 0x24 Current DMA address Current CURR_ADDR 0x28 Interrupt status register con- Control/ IRQ_STATUS tains completion and DMA Status error interrupt status and channel state (run/fetch/paused) ADSP-BF59x Blackfin Processor Hardware Reference 5-63...
Page 164  The generic MMR names shown in Table 5-6 are not actually mapped to resources in the processor. For convenience, discussions in this chapter use generic (non-peripheral specific) DMA and memory DMA register names. 5-64 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 165 Because confusion might arise between descriptor element names and generic DMA register names, this chapter uses different naming conven- tions for physical registers and their corresponding elements in descriptors that reside in memory. Table 5-6 shows the relation. ADSP-BF59x Blackfin Processor Hardware Reference 5-65...
Page 166: Dma Peripheral Map Registers Dmax_Peripheral_Map
Assume that channels 6 and 7 are involved. 1. Make sure DMA is disabled on channels 6 and 7. 2. Write with 0x7000 and DMA6_PERIPHERAL_MAP with 0x6000. DMA7_PERIPHERAL_MAP 3. Enable DMA on channels 6 and/or 7. 5-66 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 167: Dma Configuration Registers (Dmax_Config/Mdma_Yy_Config)
0 - Interrupt after completing SYNC (Work Unit whole buffer (outer loop) Transitions) 1 - Interrupt after completing 0 - Continuous transition each row (inner loop) 1 - Synchronized transition Figure 5-6. DMA Configuration Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-67...
Page 168 NDPH fore, the high 16 bits of the next descriptor pointer field are taken from the upper 16 bits of the register, thus DMAx_NEXT_DESC_PTR confining all descriptors to a specific 64K page in memory. 5-68 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 169 Work unit transitions for MDMA streams are controlled by the bit of the MDMA source channel’s register. The SYNC DMAx_CONFIG bit of the MDMA destination channel is reserved and must be SYNC set to 0. ADSP-BF59x Blackfin Processor Hardware Reference 5-69...
Page 170 DMA unit ignores the peripheral interrupt and passes it directly to the interrupt controller. To avoid unexpected results, take care to enable the DMA channel before enabling the peripheral, and to disable the peripheral before disabling the DMA channel. 5-70 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 171 For MDMA transfers where an interrupt is not desired to notify when the DMA operation has ended, software should poll the bit, rather than the bit to determine when the DMA_DONE DMA_RUN transaction has completed. ADSP-BF59x Blackfin Processor Hardware Reference 5-71...
Page 172: Dma Interrupt Status Registers (Dmax_Irq_Status/Mdma_Yy_Irq_Status)
The DMA error conditions for all DMA channels are OR’d together into one system-level DMA error interrupt. The individual words IRQ_STATUS of each channel can be read to identify the channel that caused the DMA error interrupt. 5-72 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 173 When switching a peripheral from DMA to non-DMA mode, the peripheral’s interrupts should be disabled during the mode switch (via the appropriate peripheral register or register) so SIC_IMASK that no unintended interrupt is generated on the shared DMA/interrupt request line. ADSP-BF59x Blackfin Processor Hardware Reference 5-73...
Page 174: Dma Start Address Registers
DMA transfer address for a given DMA session. On the first mem- ory transfer of a DMA work unit, the register is loaded DMAx_CURR_ADDR from the register, and it is incremented as each transfer DMAx_START_ADDR occurs. 5-74 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 175: Dma Inner Loop Count Registers
15 14 13 12 11 10 Reset = Undefined X_COUNT[15:0] (Inner Loop Count) The number of elements to transfer (1-D); the number of rows in the inner loop (2-D) Figure 5-10. DMA Inner Loop Count Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-75...
Page 176: Dma Current Inner Loop Count Registers
CURR_X_COUNT[15:0] (Current Inner Loop Count) Loaded by X_COUNT at the beginning of each DMA session (1-D DMA), or at the beginning of each row (2-D DMA) Figure 5-11. DMA Current Inner Loop Count Registers 5-76 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 177: Dma Inner Loop Address Increment Registers
R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined X_MODIFY[15:0] (Inner Loop Address Increment) Stride (in bytes) to take after each decrement of CURR_X_COUNT Figure 5-12. DMA Inner Loop Address Increment Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-77...
Page 178: Dma Outer Loop Count Registers
DMAx_CURR_X_COUNT 2-D DMA operation (1 to or 1 to 0 transition), signifying DMAx_X_COUNT completion of an entire row transfer. After a 2-D DMA session is com- plete, = 1 and = 0. DMAx_CURR_Y_COUNT DMAx_CURR_X_COUNT 5-78 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 179 R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined Y_MODIFY[15:0] (Outer Loop Address Increment) Stride to take after each decre- ment of CURR_Y_COUNT Figure 5-15. DMA Outer Loop Address Increment Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-79...
Page 180 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined Next Descriptor Pointer[31:16] 15 14 13 12 11 10 Next Descriptor Pointer[15:0] Figure 5-16. DMA Next Descriptor Pointer Registers 5-80 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 181: Dma Next Descriptor Pointer Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined Next Descriptor Pointer[31:16] 15 14 13 12 11 10 Next Descriptor Pointer[15:0] Figure 5-17. DMA Current Descriptor Pointer Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-81...
Page 182: Hmdma Registers
BCOUNT BCINIT while the module is already active. Do not set this bit in the same write that sets the bit to active. HMDMAEN 5-82 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 183 10 - Request multiple transfers from MDMA channel (default) 1 - Interrupt generated when 11 - Request urgent multiple transfers from MDMA channel BCOUNT decrements to 0 and ECOUNT = 0 Figure 5-18. Handshake MDMA Control Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-83...
Page 184: Handshake Mdma Initial Block Count Registers
MBDI HMDMAx_CONTROL until is 0. If is 0, no interrupt is generated, ECOUNT BCINIT block done since no DMA requests were generated or grants received. 5-84 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 185: Handshake Mdma Current Edge Count Registers (Hmdmax_Ecount)
• 0x8000 = –32,768: ignore the next 32,768 edges Each time that expires, is decremented and BCOUNT ECOUNT BCOUNT reloaded from . When a handshake request edge is detected, BCINIT ECOUNT is incremented. The field is cleared when is disabled. ECOUNT HMDMA ADSP-BF59x Blackfin Processor Hardware Reference 5-85...
Page 186: Handshake Mdma Initial Edge Count Registers
Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) 15 14 13 12 11 10 Reset = 0x0000 ECINIT[15:0] (Initial Edge Count) Figure 5-22. Handshake MDMA Initial Edge Count Registers 5-86 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 187: Handshake Mdma Edge Count Urgent Registers
Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) 15 14 13 12 11 10 Reset = 0xFFFF ITHR[15:0] (Interrupt Threshold) Figure 5-24. Handshake MDMA Edge Count Overflow Interrupt Registers ADSP-BF59x Blackfin Processor Hardware Reference 5-87...
Page 188: Dma Traffic Control Registers
MDMA stream is granted, or whenever every MDMA stream is idle. It then counts down to 0 with each MDMA transfer. When this count decrements from 1 to 0, the next available MDMA stream is selected. 5-88 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 189 1 to 0, the opposite direction DEB access is treated preferentially, which may result in a direction change. When this count is 0 and a DEB bus access occurs, the count is reloaded from to begin a new burst. DEB_TRAFFIC_PERIOD ADSP-BF59x Blackfin Processor Hardware Reference 5-89...
Page 190: Programming Examples
26 27 28 29 Figure 5-27. DMA Example, 2-D Array The two arrays reside in two different L1 data memory blocks. However, the arrays could reside in any internal or external memory, including L1 5-90 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 191 = lo(MDMA_S0_CONFIG); p0.h = hi(MDMA_S0_CONFIG); call memdma_setup; call memdma_wait; _main.forever: jump _main.forever; _main.end: The setup routine shown in Listing 5-2 initializes either MDMA0 or MDMA1, depending on whether the MMR address of MDMA_S0_CONFIG ADSP-BF59x Blackfin Processor Hardware Reference 5-91...
Page 192 = -2 * (Y * (X-1) - 1); w[p0 + MDMA_D0_Y_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = DMA2D | DI_EN | WDSIZE_16 | WNR | DMAEN; w[p0 + MDMA_D0_CONFIG - MDMA_S0_CONFIG] = r7; r7 = [sp++]; 5-92 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 193: Initializing Descriptors In Memory
DMA descriptors. This example has two descriptors in small list flow mode that point to each other. At the end of the second work unit, an interrupt is generated without discontinuing the DMA processing. The ADSP-BF59x Blackfin Processor Hardware Reference 5-93...
Page 194 Another method featured by the VisualDSP++ tools takes advantage of C-style structures in global header files. The header file descriptors.h could look like Listing 5-5. Listing 5-5. Header File to Define Descriptor Structures #ifndef __INCLUDE_DESCRIPTORS__ #define __INCLUDE_DESCRIPTORS__ #ifdef _LANGUAGE_C typedef struct { 5-94 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 195 C-style header file and can finally take advantage of the structures. See Listing 5-6. Listing 5-6. Using Descriptor Structures #include "descriptors.h" .import "descriptors.h"; .section L1_data_a; .align 4; .var arrBlock3[N]; ADSP-BF59x Blackfin Processor Hardware Reference 5-95...
Page 196: Software-Triggered Descriptor Fetch Example
Note the requirement that source and destination channels stop after the same number of transfers. Between stops, the two channels can have com- pletely individual structures. Listing 5-7. Software-Triggered Descriptor Fetch .import "descriptors.h"; 5-96 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 197 0, 0 /* unused values */ .struct dma_desc_list descDest1 = { descDest2, arrDest1, DI_EN | WDSIZE_16 | WNR | DMAEN, length(arrDest1), 2, 0, 0 /* unused values */ .struct dma_desc_list descDest2 = { descDest1, arrDest2, ADSP-BF59x Blackfin Processor Hardware Reference 5-97...
Page 198 CC = bittst (r0, bitpos(DMA_DONE)); if !CC jump _main.wait; r0.l = DMA_DONE; w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] = r0; /* wait for any software or hardware event here */ /* start next work unit */ 5-98 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 199: Handshaked Memory Dma Example
/* function enable for DMAR1 */ p1.l = lo(PORTG_FER); r0.l = PG12; w[p1] = r0; p1.l = lo(PORTG_MUX); r0.l = 0x0000; w[p1] = r0; /* every single transfer requires one DMAR1 event */ p1.l = lo(HMDMA1_BCINIT); ADSP-BF59x Blackfin Processor Hardware Reference 5-99...
Page 200 This is because the transmit channel still has to drain the DMA FIFO. Listing 5-9. HMDMA With Delayed Processing /* wait for eight requests */ p1.l = lo(HMDMA1_ECOUNT); r0 = 7 (z); initial_requests: r1 = w[p1] (z); 5-100 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 201: Unique Information For The Adsp-Bf59X Processor
Static Channel Prioritization The default DMA channel priority and mapping shown in Table 5-9 on page 5-103 can be changed by altering the 4-bit PMAP field in the registers for the peripheral DMA channels. DMAx_PERIPHERAL_MAP ADSP-BF59x Blackfin Processor Hardware Reference 5-101...
Page 202 IRQ 10 DMA 2 CONTROL FIFO PMAP IRQ 9 DMA 1 CONTROL FIFO PMAP IRQ 8 DMA 0 CONTROL FIFO PMAP 3 x 12 DAB DGT DRQ Figure 5-28. ADSP-BF59x DMA Controller Block Diagram 5-102 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 203 Mem DMA has no peripheral mapping. MDMA S0 None Mem DMA has no peripheral mapping. MDMA D1 None Mem DMA has no peripheral mapping. Lowest MDMA S1 None Mem DMA has no peripheral mapping. ADSP-BF59x Blackfin Processor Hardware Reference 5-103...
Page 204 Unique Information for the ADSP-BF59x Processor 5-104 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 205: Dynamic Power Management
PLL with a multiplication factor for . The CLKIN resulting, multiplied signal is the voltage controlled oscillator (VCO) clock. A user-programmable value then divides the VCO clock signal to generate the core clock ( CCLK ADSP-BF59x Blackfin Processor Hardware Reference...
Page 206: Pll Overview
6-7. Subject to the maximum VCO frequency specified in the processor data sheet, the PLL supports a wide range of multiplier ratios and achieves multiplication of the input clock, . To achieve this wide CLKIN ADSP-BF59x Blackfin Processor Hardware Reference...
Page 207: Pll Clock Multiplier Ratios
CCLK = SCLK = CLKIN Figure 6-1. PLL Block Diagram PLL Clock Multiplier Ratios The PLL control register ( ) governs the operation of the PLL. For PLL_CTL details about the register, see “PLL_CTL Register” on page 6-20. PLL_CTL ADSP-BF59x Blackfin Processor Hardware Reference...
Page 208 PLL_CTL not take effect immediately. In general, the register is first pro- PLL_CTL grammed with a new value, and then a specific PLL programming sequence must be executed to implement the changes. This is handled ADSP-BF59x Blackfin Processor Hardware Reference...
Page 209: Core Clock/System Clock Ratio Control
PLL_CTL PLL_DIV grammed at any time to change the divide values without CCLK SCLK entering the PLL programing sequence. Table 6-2. Core Clock Ratio Signal Name Divider Ratio Example Frequency Ratios (MHz) CSEL[1:0] VCO/CCLK CCLK ADSP-BF59x Blackfin Processor Hardware Reference...
Page 210 PLL_LOCKCNT bit is set. PLL_LOCKED See the processor data sheet for more information about PLL stabilization time and programmed values for this register. For more information about operating modes, see “Operating Modes” on page 6-7. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 211: Dynamic Power Management Controller
Access Full On None Enabled Enabled Enabled Active Medium Enabled Enabled Enabled Sleep High Enabled Disabled Enabled – Deep Sleep Maximum Disabled – Disabled Disabled – 1 PLL can also be disabled in this mode. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 212: Dynamic Power Management Controller States
In active mode, it is possible not only to bypass, but also to disable the PLL. If disabled, the PLL must be re-enabled before transitioning to full- on or sleep modes. From active mode, the processor can transition directly to full-on, sleep, or deep sleep modes. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 213: Sleep Mode
If an interrupt is also enabled in , the SIC_IMASK interrupt is vectored immediately after exit of deep sleep, and the related ISR executed. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 214: Hibernate State
) register that must be changed for the PLL_CTL transition to occur. For example, the transition from full-on mode to sleep mode indicates that the bit must be set to 1 and the bit must STOPCK PDWN be set to 0. 6-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 215 To re-enable the PLL, clear the PLL_OFF in the register, and then execute the PLL programming PLL_CTL sequence. • New multiplier ratio: The multiplier ratio can also be changed while in full-on mode. ADSP-BF59x Blackfin Processor Hardware Reference 6-11...
Page 216 HIBERNATEB = 0 HARDWARE RESET MSEL = new value & PLL_OFF = 0 & BYPASS = 0 Hibernate Reset HIBERNATEB = 0 HARDWARE RESET GPIO ASSERTION & GPIO WAKEUP ENABLED Figure 6-2. Operating Mode Transitions 6-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 217: Programming Operating Mode Transitions
VCO multiplier or PLL_CTL CLKIN power is reapplied to the PLL, the PLL needs to relock. To relock, the PLL lock counter is cleared first, then starts incrementing once per SCLK ADSP-BF59x Blackfin Processor Hardware Reference 6-13...
Page 218 If the register is programmed to enter the deep sleep operating PLL_CTL mode, the processor immediately transitions to deep sleep mode and waits for a hardware reset signal or GPIO wakeup: 6-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 219: Dynamic Supply Voltage Control
Note that the external regulator must comply with the V specifications defined in DDINT the processor data sheet. Changing Voltage When changing the voltage using an external regulator, a specific pro- gramming sequence must be followed. ADSP-BF59x Blackfin Processor Hardware Reference 6-15...
Page 220 (CCLK), are within the limits specified in the processor data sheet for the new operating voltage level. 6-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 221: Powering Down The Core (Hibernate State)
EXT_WAKE is an output pin, which is a logical OR of the above EXT_WAKE wakeup sources, except hardware reset. The pin follows the wakeup signal of the various wakeup sources. ADSP-BF59x Blackfin Processor Hardware Reference 6-17...
Page 222: Pll And Vr Registers
The user interface to the PLL and VR registers is through the system con- trol ROM function ( ) described in “System Control bfrom_SysControl() ROM Function” on page 6-22. The memory-mapped registers (MMRs) are shown in Table 6-7 and illustrated in Figure 6-3 through Figure 6-7. 6-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 223: Pll_Div Register
0 - Reserved 01 - CCLK = VCO / 2 1-15 - SCLK = VCO / X 10 - CCLK = VCO / 4 11 - CCLK = VCO / 8 Figure 6-3. PLL Divide Register ADSP-BF59x Blackfin Processor Hardware Reference 6-19...
Page 224: Pll_Ctl Register
Reset = 0x00A2 0xFFC0 000C VSTAT ACTIVE_PLLENABLED 0: Voltage regulator is not stable. 1: Voltage regulator is stable. FULL_ON PLL_LOCKED ACTIVE_PLLDISABLED For more information, see “Operating Modes” on page 6-7. Figure 6-5. PLL Status Register 6-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 225: Pll_Lockcnt Register
1 - PG1 event wakeup enabled 1- Writing 1 has no effect. Figure 6-7. Voltage Regulator Control Register The external clock select ( ) control bit configures the EXTCLK_SEL EXTCLK ADSP-BF59x Blackfin Processor Hardware Reference 6-21...
Page 226: System Control Rom Function
C-language style calling conventions. Entry address: 0xEF00 0038 Arguments: • word in dActionFlags • pointer in pSysCtrlSettings • zero value in A potential error message of internally called function bfrom_OtpRead() forwarded and returned in 6-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 227 ADI_SYSCTRL_VALUES *pSysCtrlSettings system control ROM function passes a pointer to a special structure, which has entries for all PLL and voltage regulator registers. It is pre- defined in the header file as follows. bfrom.h ADSP-BF59x Blackfin Processor Hardware Reference 6-23...
Page 228: Programming Model
PLL_DIV PLL_CTL instruction flag along with the SYSCTRL_READ SYSCTRL_PLLCTL register flags. The function then only SYSCTRL_PLLDIV bfrom_OtpRead() updates the variables: uwPllCtl uwPllDiv ADI_SYSCTRL_VALUES read; bfrom_SysControl (SYSCTRL_READ | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV, &read, NULL) 6-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 229: Accessing The System Control Rom Function In Assembly
.STRUCT ADI_SYSCTRL_VALUES dpm = { 0x3000, 0x0C00, 0x0004, 0x0200, 0x00A2 }; or load the values dynamically inside the code: P5.H = hi(dpm); P5.L = lo(dpm->uwVrCtl); R7 = 0x3000 (z); w[P5] = R7; P5.L = lo(dpm->uwPllCtl); ADSP-BF59x Blackfin Processor Hardware Reference 6-25...
Page 230 /* Allocate at least 12 bytes on the stack for outgoing argu- ments, even if the function being called requires less than this. SP += -12; R0 = SYSCTRL_WRITE SYSCTRL_VRCTL SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL SYSCTRL_PLLDIV 6-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 231 /* Allocate at least 12 bytes on the stack for outgoing argu- ments, even if the function being called requires less than this. SP += -12; R7 = 0; R7.L = 0x3000; w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwVrCtl)] = R7; R7.L = 0x0C00; w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R7; ADSP-BF59x Blackfin Processor Hardware Reference 6-27...
Page 232: Programming Examples
P5.H = hi(BFROM_SYSCONTROL); P5.L = lo(BFROM_SYSCONTROL); call(P5); SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; Programming Examples The following code examples illustrate how to use the system control ROM function to effect various operating mode transitions. 6-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 233 • Logical voltage level ( ) is at 1.20 V VDDINT For operating mode transition and voltage regulator examples: • C • #include <blackfin.h> • #include <bfrom.h> • Assembly • #include <blackfin.h> • #include <bfrom.h> • .IMPORT "bfrom.h"; ADSP-BF59x Blackfin Processor Hardware Reference 6-29...
Page 234: Full-On Mode To Active Mode And Back
SYSCTRL_PLLCTL, &active, NULL); return; Listing 6-2. Transitioning from Full-on Mode to Active Mode (ASM) __active: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:0); SP += -12; R0 = (SYSCTRL_READ | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL); R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); 6-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 235 R2 = 0 (z); IMM32(P4,BFROM_SYSCONTROL); call(P4); SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; __active.end: To return from active mode (go back to full-on mode), the bit and BYPASS bit must be cleared again, respectively. PLL_OFF ADSP-BF59x Blackfin Processor Hardware Reference 6-31...
Page 236: Transition To Sleep Mode Or Deep Sleep Mode
Listing 6-4. Transitioning to Sleep Mode or Deep Sleep Mode (ASM) __sleep: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:0); SP += -12; R0 = (SYSCTRL_READ | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL); R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); R2 = 0 (z); IMM32(P4,BFROM_SYSCONTROL); 6-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 237: Set Wakeup Events And Enter Hibernate State
( , and ) and placing the regulator in the hiber- PG12 nate state in C and processor assembly code, respectively. Listing 6-5. Configuring Regulator Wakeups and Entering Hibernate ADSP-BF59x Blackfin Processor Hardware Reference 6-33...
Page 238 WAKE_EN2 | /* PG12 Wake-Up Enable */ WAKE_EN3 | /* PG1 Wake-Up Enable */ HIBERNATE; / *Powerdown */ w[FP+-sizeof(ADI_SYSCTRL_VALUES)+ offsetof(ADI_SYSCTRL_VALUES,uwVrCtl)] = R0; R0 = (SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_EXTVOLTAGE); R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); 6-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 239: Perform A System Reset Or Soft-Reset
NULL, NULL); /* either */ bfrom_SysControl(SYSCTRL_SOFTRESET, NULL, NULL); /* or */ return; Listing 6-8. Execute a System Reset or a Soft-Reset (ASM) __reset: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:0); SP += -12; R0 = SYSCTRL_SYSRESET; /* either */ ADSP-BF59x Blackfin Processor Hardware Reference 6-35...
Page 240: In Full-On Mode, Change Vco Frequency, Core Clock Frequency, And System Clock Frequency
/* Set MSEL = 5-63 --> VCO = CLKIN*MSEL */ frequency.uwPllCtl = SET_MSEL(21) ; /* Set SSEL = 1-15 --> SCLK = VCO/SSEL */ /* CCLK = VCO / 1 */ frequency.uwPllDiv = SET_SSEL(4) | CSEL_DIV1 6-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 241 R0.L = SET_SSEL(4) | /* Set SSEL = 1-15 --> SCLK = VCO/SSEL */ CSEL_DIV1 ; /* CCLK = VCO / 1 */ w[FP+-sizeof(ADI_SYSCTRL_VALUES)+ offsetof(ADI_SYSCTRL_VALUES,uwPllDiv)] = R0; R0.L = 0x0200; w[FP+-sizeof(ADI_SYSCTRL_VALUES)+ offsetof(ADI_SYSCTRL_VALUES,uwPllLockCnt)] = R0; /* argument 1 in R0 */ ADSP-BF59x Blackfin Processor Hardware Reference 6-37...
Page 242: Changing Voltage Levels
C code for changing the voltage level dynamically. The User must include his own code for accessing the external voltage regulator. Listing 6-11. Changing Core Voltage (C) void voltage(void) ADI_SYSCTRL_VALUES voltage; u32 ulCnt = 0; 6-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 243 0x0200 CLKIN cycles that represent PLL_LOCKCNT and addition- ally the time required by the circuitry */ ulCnt = 0x0200 + 0x0200; while (ulCnt != 0) {ulCnt--;} init.uwPllCtl &= ~BYPASS; bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_EXTVOLTAGE, &voltage, NULL); return; ADSP-BF59x Blackfin Processor Hardware Reference 6-39...
Page 244 Programming Examples 6-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 245: General-Purpose Ports
The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The ADSP-BF59x Blackfin processors feature a rich set of peripherals, which, through a powerful pin multiplexing scheme, provides great flexi- bility to the external application space.
Page 246: Interface Overview
In this chapter, the naming convention for registers and bits uses a lowercase to represent F or G. For example, the name PORTx_FER represents . The bit name represents PORTF_FER PORTG_FER . This convention is used to discuss registers common to these ports. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 247: External Interface
Bit 3 RFS1 PPI11 Bit 4 DT1SEC PPI12 Bit 5 DT1PRI PPI13 Bit 6 TSCLK1 PPI14 Bit 7 TFS1 PPI15 Bit 8 TMR2 SPI0SSEL2 WAKEN0 Bit 9 TMR0 PPI_FS1 SPI0SSEL3 Bit 10 Reserved TMR1 PPI_FS2 PF10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 248: Port G Structure
Bit 0 DR0SEC SPI0SSEL1 SPI0SS Bit 1 DR0PRI SPI1SSEL1 WAKEN3 Bit 2 RSCLK0 SPI0SSEL5 Bit 3 RFS0 PPI_FS3 Bit 4 DT0SEC SPI0SSEL6 HWAIT Bit 5 DT0PRI SPI1SSEL6 Bit 6 Reserved TSCLK0 Bit 7 TFS0 SPI1SSEL7 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 249: Additional Considerations
PPI_FS2 TMR1 avoid possible erroneous behavior associated with ringing if out- puts are not well terminated. Whenever inputs are TMR0 TMR1 used, must be separately specified as the clock input for PPI_CLK the associated timer. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 250: Internal Interfaces
PORTF_FER PORTG_FER peripheral functionality for each individual pin of a port. Performance/Throughput pins are synchronized to the system clock ( ). When SCLK configured as outputs, the GPIOs can transition once every system clock cycle. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 251: Description Of Operation
When the control bit in the function enable registers ( ) is set, PORTx_FER the pin is set to its peripheral functionality and is no longer controlled by the GPIO module. However, the GPIO module can still sense the state of ADSP-BF59x Blackfin Processor Hardware Reference...
Page 252: General-Purpose I/O Modules
GPIO that is being used as an input. Leaving the input buffer disabled eliminates the need for pull-ups and pull-downs when a particular pin is not used in the system. By default, the input buffers are disabled. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 253 The state of the output is reflected on the associated pin only if the func- tion enable bit in the register is cleared. PORTx_FER ADSP-BF59x Blackfin Processor Hardware Reference...
Page 254 GPIO latch. This is usually performed through the clear registers. Read operations from the GPIO clear registers return the content of the GPIO data registers. 7-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 255: Gpio Interrupt Processing
(low to high and high to low). Input sensitivity is defined on a per-bit basis by the GPIO polarity registers ( PORTFIO_POLAR ), and the GPIO interrupt sensitivity registers PORTGIO_POLAR ). If configured for edge sensitivity, the PORTFIO_EDGE PORTGIO_EDGE ADSP-BF59x Blackfin Processor Hardware Reference 7-11...
Page 256 The interrupt service routine should clear the GPIO to acknowledge the request. Each of the two GPIO modules provides two independent interrupt chan- nels. Identical in functionality, these are called interrupt A and interrupt 7-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 257 While a direct write to a mask interrupt register alters all bits in the register, writes to a mask interrupt set register can be used to set a single or a few bits only. No read-modify-write operations are required. ADSP-BF59x Blackfin Processor Hardware Reference 7-13...
Page 258 Figure 7-1. GPIO Interrupt Generation Flow for Interrupt Channel A The mask interrupt set registers are write-1-to-set registers. All ones con- tained in the value written to the mask interrupt set register set the 7-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 259 All GPIOs assigned to the same interrupt channel are OR’ed. If multiple GPIOs are assigned to the same interrupt channel, it is up to the interrupt service routine to evaluate the GPIO data registers to determine the sig- naling interrupt source. ADSP-BF59x Blackfin Processor Hardware Reference 7-15...
Page 260 Description of Operation Figure 7-2 shows the mapping of the four GPIO interrupt channels of port F and port G. IRQ17 PORTFIO_MASKA_D IRQ18 PORTFIO_MASKB_D PORTGIO_MASKA_D IRQ22 IRQ23 PORTGIO_MASKB_D Figure 7-2. GPIO Interrupt Channels 7-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 261: Programming Model
BITS TO ENABLE INPUT DRIVERS DIRECTION WRITE PORTxIO_CLEAR TO SET APPROPRIATE BITS TO LOWER INDIVIDUAL GPIO WRITE PORTxIO_SET TO SET APPROPRIATE BITS TO RAISE INDIVIDUAL GPIO Figure 7-3. GPIO Flow Chart (Part 1 of 2) ADSP-BF59x Blackfin Processor Hardware Reference 7-17...
Page 262 PORTxIO_MASKB_SET, PORTxIO_MASKA_TOGGLE, OR PORTxIO_MASKB_TOGGLE TO SET APPROPRIATE BITS ON WHICH TO GENERATE AN INTERRUPT INTERRUPTS MUST THEN BE CONFIGURED AT THE SYSTEM INTERRUPT CONTROLLER AND CORE EVENT CONTROLLER Figure 7-4. GPIO Flow Chart (Part 2 of 2) 7-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 263: Gpio Schmitt Trigger Control
1 - Enable PF11/12 Hysteresis FPADCTL6 0 - Disable PF13/14 Hysteresis 1 - Enable PF13/14 Hysteresis FPADCTL7 0 - Disable PF15 Hysteresis 1 - Enable PF15 Hysteresis Figure 7-5. Port F Pad Control (Hysteresis) Register ADSP-BF59x Blackfin Processor Hardware Reference 7-19...
Page 264: Memory-Mapped Gpio Registers
The GPIO registers are part of the system memory-mapped registers (MMRs). Figure 7-7 through Figure 7-25 on page 7-33 illustrate the GPIO registers. The addresses of the programmable flag MMRs appear in “System MMR Assignments” on page A-1. 7-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 265: Port Multiplexer Control Register (Portx_Mux)
0 = Peripheral function 1 = Alternate peripheral function Refer to Table 7-1 on page 7-3 Table 7-2 on page 7-4 for reserved bits in the PORTx_MUX register. Figure 7-7. Port Multiplexer Control Register ADSP-BF59x Blackfin Processor Hardware Reference 7-21...
Page 266: Function Enable Registers (Portx_Fer)
Px1 Direction Px2 Direction Px3 Direction Px15 Direction Px4 Direction Px14 Direction Px5 Direction Px13 Direction Px6 Direction Px12 Direction Px7 Direction Px11 Direction Px8 Direction Px10 Direction Px9 Direction Figure 7-9. GPIO Direction Registers 7-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 267: Gpio Data Registers (Portxio)
Program Px1 Program Px2 Program Px3 Program Px15 Program Px4 Program Px14 Program Px5 Program Px13 Program Px6 Program Px12 Program Px7 Program Px11 Program Px8 Program Px10 Program Px9 Figure 7-11. GPIO Data Registers ADSP-BF59x Blackfin Processor Hardware Reference 7-23...
Page 268: Gpio Set Registers (Portxio_Set)
Clear Px1 Clear Px2 Clear Px3 Clear Px15 Clear Px4 Clear Px14 Clear Px5 Clear Px13 Clear Px6 Clear Px12 Clear Px7 Clear Px11 Clear Px8 Clear Px9 Clear Px10 Figure 7-13. GPIO Clear Registers 7-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 269: Gpio Toggle Registers (Portxio_Toggle)
Px1 Polarity Px2 Polarity Px3 Polarity Px15 Polarity Px4 Polarity Px14 Polarity Px5 Polarity Px13 Polarity Px6 Polarity Px12 Polarity Px7 Polarity Px11 Polarity Px8 Polarity Px10 Polarity Px9 Polarity Figure 7-15. GPIO Polarity Registers ADSP-BF59x Blackfin Processor Hardware Reference 7-25...
Page 270: Interrupt Sensitivity Registers (Portxio_Edge)
Px5 Both Edges Px13 Both Edges Px6 Both Edges Px12 Both Edges Px7 Both Edges Px11 Both Edges Px8 Both Edges Px10 Both Edges Px9 Both Edges Figure 7-17. GPIO Set on Both Edges Registers 7-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 271: Gpio Mask Interrupt Registers (Portxio_Maska/B)
Enable Px6 Interrupt B Enable Px12 Interrupt B Enable Px7 Interrupt B Enable Px11 Interrupt B Enable Px8 Interrupt B Enable Px10 Interrupt B Enable Px9 Interrupt B Figure 7-19. GPIO Mask Interrupt B Registers ADSP-BF59x Blackfin Processor Hardware Reference 7-27...
Page 272: Gpio Mask Interrupt Set Registers (Portxio_Maska/B_Set)
Set Px11 Interrupt A Enable Enable Set Px7 Interrupt A Set Px10 Interrupt A Enable Enable Set Px8 Interrupt A Enable Set Px9 Interrupt A Enable Figure 7-20. GPIO Mask Interrupt A Set Registers 7-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 273 Set Px11 Interrupt B Enable Enable Set Px7 Interrupt B Set Px10 Interrupt B Enable Enable Set Px8 Interrupt B Enable Set Px9 Interrupt B Enable Figure 7-21. GPIO Mask Interrupt B Set Registers ADSP-BF59x Blackfin Processor Hardware Reference 7-29...
Page 274: Gpio Mask Interrupt Clear Registers (Portxio_Maska/B_Clear)
Clear Px11 Interrupt A Enable Enable Clear Px7 Interrupt A Clear Px10 Interrupt A Enable Enable Clear Px8 Interrupt A Enable Clear Px9 Interrupt A Enable Figure 7-22. GPIO Mask Interrupt A Clear Registers 7-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 275 Clear Px11 Interrupt B Enable Enable Clear Px7 Interrupt B Clear Px10 Interrupt B Enable Enable Clear Px8 Interrupt B Enable Clear Px9 Interrupt B Enable Figure 7-23. GPIO Mask Interrupt B Clear Registers ADSP-BF59x Blackfin Processor Hardware Reference 7-31...
Page 276: Gpio Mask Interrupt Toggle Registers (Portxio_Maska/B_Toggle)
Enable Toggle Px6 Interrupt A Toggle Px10 Interrupt A Enable Enable Toggle Px7 Interrupt A Enable Toggle Px8 Interrupt A Enable Toggle Px9 Interrupt A Enable Figure 7-24. GPIO Mask Interrupt A Toggle Registers 7-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 277: Programming Examples
Listing 7-1. General-Purpose Ports /* set port f function enable register to GPIO (not peripheral) p0.l = lo(PORTF_FER); p0.h = hi(PORTF_FER); R0.h = 0x0000; r0.l = 0x0000; w[p0] = r0; ADSP-BF59x Blackfin Processor Hardware Reference 7-33...
Page 278 = lo(PORTFIO_INEN); p0.h = hi(PORTFIO_INEN); r0.h = 0x0000; r0.l = 0x003C; w[p0] = r0; ssync; /* set port f polarity register */ p0.l = lo(PORTFIO_POLAR); p0.h = hi(PORTFIO_POLAR); r0 = 0x00000; w[p0] = r0; ssync; 7-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 279: General-Purpose Timers
GP timer behavior for the ADSP-BF59x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF59x Processor” on page 8-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 280: Overview
• Unused timers can function as edge-sensitive pin interrupts The internal structure of the individual timers is illustrated by Figure 8-1, which shows the details of timer 0 as a representative example. The other timers have identical structure. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 281: External Interface
When clocked internally, the clock source is the processor’s peripheral clock ( ). Assuming the peripheral clock is running at 100 MHz, the SCLK maximum period for the timer count is ((2 -1) / 100 MHz) = 42.9 seconds. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 282: Internal Interface
TIMIL TIMER_STATUS set and issue a system interrupt request. The latches TOVF_ERR TIMIL are sticky and should be cleared by software using W1C (write-1-to-clear) operations to clear the interrupt request. The global register TIMER_STATUS ADSP-BF59x Blackfin Processor Hardware Reference...
Page 283: Interrupt Processing
The timer status ( ) register latches the timer inter- TIMER_STATUS rupts to provide a means for software to determine the interrupt source. Figure 8-2 shows the interrupt structure of the timers. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 284 Figure 8-2. Timers Interrupt Structure To enable interrupt generation, set the bit and unmask the inter- IRQ_ENA rupt source in the registers. To poll the IMASK SIC_IMASK TIMIL without interrupt generation, set but leave the interrupt masked IRQ_ENA ADSP-BF59x Blackfin Processor Hardware Reference...
Page 285: Illegal States
• Startup. The first clock period during which the timer counter is running after the timer is enabled by writing TIMER_ENABLE • Rollover. The time when the current count matches the value in and the counter is reloaded with the value "1". TIMER_PERIOD ADSP-BF59x Blackfin Processor Hardware Reference...
Page 286 ERR_TYP is __.” TOVF_ERR  Startup error conditions do not prevent the timer from starting. Similarly, overflow and rollover error conditions do not stop the timer. Illegal cases may cause unwanted behavior of the pin. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 287 ≥ Anything change change Rollover Rollover is not possible in this mode. Overflow, not possible Anything Anything b#01 unless there is also another error, such as TIMER_WIDTH == 0 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 288: Modes Of Operation
Pulse Width Modulation (PWM_OUT) Mode Use the mode for PWM signal or single-pulse generation, for PWM_OUT interval timing or for periodic interrupt generation. Figure 8-3 illustrates mode. PWM_OUT 8-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 289 = 0). PERIOD_CNT DATA BUS TIMER_PERIOD TIMER_WIDTH TMRCLK PWM_CLK CLOCK RESET TACLK TIMER_COUNTER SCLK TIN_SEL CLK_SEL EQUAL? EQUAL? TIMER_ENABLE ASSERT DEASSERT PULSE_HI PWMOUT TOGGLE_HI LOGIC OUT_DIS INTERRUPT PERIOD_CNT Figure 8-3. Timer Flow Diagram, PWM_OUT Mode ADSP-BF59x Blackfin Processor Hardware Reference 8-11...
Page 290: Output Pad Disable
Single Pulse Generation If the bit is cleared, the mode generates a single pulse PERIOD_CNT PWM_OUT on the pin. This mode can also be used to implement a precise delay. 8-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 291: Pulse Width Modulation Waveform Generation
Pulse Width Modulation Waveform Generation If the bit is set, the internally clocked timer generates rectan- PERIOD_CNT gular signals with well-defined period and duty cycle (PWM patterns). This mode also generates periodic interrupts for real-time signal processing. ADSP-BF59x Blackfin Processor Hardware Reference 8-13...
Page 292 ( ) and TIMIL might alter period and/or width values. In PWM applications, the soft- ware needs to update period and pulse width values while the timer is 8-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 293: Pulse_Hi Toggle Mode
(via the register). When two or more timers are running synchro- TIMER_WIDTH nously by the same period settings, the pulses are aligned to the asserting edge as shown in Figure 8-6. ADSP-BF59x Blackfin Processor Hardware Reference 8-15...
Page 294 Count = Pulse Width. The net result is an output waveform pulse that repeats every two counter periods and is centered around the end of the first period (or the start of the second period). 8-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 295 ENABLE Figure 8-7. Three Timers With Same Period Settings Similarly, two timers can generate non-overlapping clocks, by cen- ter-aligning the pulses while inverting the signal polarity for one of the timers (see Figure 8-8). ADSP-BF59x Blackfin Processor Hardware Reference 8-17...
Page 296 For example, if the pseudo-code when = 0 is: TOGGLE_HI int period, width; for (;;) { period = generate_period(...) ; width = generate_width(...) ; waitfor (interrupt) ; write (TIMER_PERIOD, period) ; write (TIMER_WIDTH, width) ; 8-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 297 TRUN TIMER_STATUS even-numbered periods in mode. When is writ- TOGGLE_HI TIMER_DISABLE ten to "1", the current pair of counter periods (one waveform period) completes before the timer is disabled. ADSP-BF59x Blackfin Processor Hardware Reference 8-19...
Page 298: Externally Clocked Pwm_Out
The alternate timer clock inputs ( ) are enabled when a timer is in TACLK mode with = 1 and = 0, without regard to the PWM_OUT CLK_SEL TIN_SEL content of the multiplexer control and function enable registers. 8-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 299: Using Pwm_Out Mode With The Ppi
It stops cleanly at the end of the first period when the enable latch is cleared. During this final period the bit returns "0", but the TIMEN bit still reads as a "1". TRUN ADSP-BF59x Blackfin Processor Hardware Reference 8-21...
Page 300 Use this feature carefully, because it may corrupt the PWM pattern generated at the pin. When a timer is disabled, the register retains its state; TIMER_COUNTER when a timer is re-enabled, the timer counter is reinitialized based on the 8-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 301: Pulse Width Count And Capture (Wdth_Cap) Mode
WDTH_CAP DATA BUS TIMER_PERIOD TIMER_WIDTH SCLK RESET TIMER_COUNTER PULSE_HI PULSE_HI LEADING TRAILING EDGE EDGE DETECT DETECT TIMER_ENABLE TOVF_ERR PERIOD_CNT INTERRUPT LOGIC INTERRUPT Figure 8-10. Timer Flow Diagram, WDTH_CAP Mode ADSP-BF59x Blackfin Processor Hardware Reference 8-23...
Page 302 (if enabled) but does not generate an error. TIMIL bit in the register controls the point in PERIOD_CNT TIMER_CONFIG time at which this set of transactions is executed. Taken together, these 8-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 303 PERIOD_CNT tured in the period buffer. Instead, an error report interrupt is generated (if enabled) when the counter range is exceeded and the counter wraps around. In this case, both read "0" TIMER_WIDTH TIMER_PERIOD ADSP-BF59x Blackfin Processor Hardware Reference 8-25...
Page 304 COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 8-11. Example of Period Capture Measurement Report Timing (WDTH_CAP mode, PERIOD_CNT = 1) 8-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 305 REPORT REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 8-12. Example of Width Capture Measurement Report Timing (WDTH_CAP mode, PERIOD_CNT = 0) ADSP-BF59x Blackfin Processor Hardware Reference 8-27...
Page 306 (a measurement report), but never both at the same time. registers are never updated at the TIMER_PERIOD TIMER_WIDTH time an error is signaled. Refer to Figure 8-13 Figure 8-14 for more information. 8-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 307 NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 8-13. Example Timing for Period Overflow Followed by Period Capture ( mode, = 1) WDTH_CAP PERIOD_CNT ADSP-BF59x Blackfin Processor Hardware Reference 8-29...
Page 308 NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 8-14. Example Timing for Width Capture Followed by Period Overflow ( mode, = 0) WDTH_CAP PERIOD_CNT 8-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 309: Autobaud Mode
TACI mode. Autobaud detection can be used for initial bit rate negoti- WDTH_CAP ations as well as for detection of bit rate drifts while the interface is in operation. ADSP-BF59x Blackfin Processor Hardware Reference 8-31...
Page 310: External Event (Ext_Clk) Mode
0xFFFF FFFF to "0" or if Period = "0" at startup or when the register rolls over (from Count = Period to TIMER_COUNTER Count = 0x1). The register is unused. TIMER_WIDTH 8-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 311: Programming Model
If this order is not followed, the plausibility check may fail because of undefined width and period values, or writes to TIMER_WIDTH may result in an error condition, because the registers are TIMER_PERIOD read-only in some modes. The timer may not start as expected. ADSP-BF59x Blackfin Processor Hardware Reference 8-33...
Page 312: Timer Registers
It consists of multiple identical timer units. Each timer provides four registers: • – timer configuration register TIMER_CONFIG[15:0] • – timer pulse width register TIMER_WIDTH[31:0] • – timer period register TIMER_PERIOD[31:0] • – timer counter register TIMER_COUNTER[31:0] 8-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 313: Timer Enable Register (Timer_Enable)
"0" has no effect. The bits can be set individually or in any combination. A read of the register shows the status of the enable for the TIMER_ENABLE corresponding timer. A "1" indicates that the timer is enabled. All unused bits return "0" when read. ADSP-BF59x Blackfin Processor Hardware Reference 8-35...
Page 314 A read of the register returns a value identical to a read of the TIMER_DISABLE register. A "1" indicates that the timer is enabled. All TIMER_ENABLE unused bits return "0" when read. 8-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 315 , and then writing a "1" to the TIMER_DISABLE corresponding bit in . See “Stopping the Timer in TRUN TIMER_STATUS PWM_OUT Mode” on page 8-21. modes, a write of a "1" to stops WDTH_CAP EXT_CLK TIMER_DISABLE the corresponding timer immediately. ADSP-BF59x Blackfin Processor Hardware Reference 8-37...
Page 316 Writing the bits TRUN to "1" in mode has no effect on a timer that has not first been PWM_OUT disabled. Error conditions are explained in “Illegal States” on page 8-7. 8-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 317 This diagram shows an example configuration for eight timers. Different products have differ- ent numbers of timers, therefore some of the bits may not be applicable to your device. Figure 8-18. Timer Status Register ADSP-BF59x Blackfin Processor Hardware Reference 8-39...
Page 318 = 01) when the bit is cleared. TMODE OUT_DIS  When operating the PPI in GP output modes with internal frame syncs, the and the bits for the timers involved CLK_SEL TIN_SEL must be set to "1". 8-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 319: Timer Configuration Register (Timer_Config)
, the pin, the SCLK alternative timer clock pin , or the common pin, which is TACLK TMRCLK most likely used as the PPI clock ( PPI_CLK ADSP-BF59x Blackfin Processor Hardware Reference 8-41...
Page 320: Timer Counter Register (Timer_Counter)
When a timer is enabled and running, and the software writes new values to the register and the register, TIMER_PERIOD TIMER_WIDTH the writes are buffered and do not update the registers until the end of the current period (when equals TIMER_COUNTER TIMER_WIDTH 8-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 321 TIMER_PERIOD TIMER_WIDTH will be ready for use in the first timer period. For example, to change the values for the and/or registers in order to use a TIMER_PERIOD TIMER_WIDTH ADSP-BF59x Blackfin Processor Hardware Reference 8-43...
Page 322 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 Timer Period[31:16] 15 14 13 12 11 10 Timer Period[15:0] Figure 8-21. Timer Period Register 8-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 323: Summary
0 - Interrupt after mea- suring width IRQ_ENA 1 - Enable interrupt 1 - Enable interrupt 1 - Enable interrupt 0 - Disable interrupt 0 - Disable interrupt 0 - Disable interrupt ADSP-BF59x Blackfin Processor Hardware Reference 8-45...
Page 324 Depends on TIN_SEL: Input OUT_DIS: 1 - Unused 1 - Three-state 0 - Input 0 - Output Period R/W: Period value RO: Period value R/W: Period value Width R/W: Width value RO: Width value Unused 8-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 325 Programming Examples Listing 8-1 configures the port control registers in a way that enables pins associated with Port G. This example assumes are connected TMR1-7 to Port G bits 5–11. Listing 8-1. Port Setup timer_port_setup: ADSP-BF59x Blackfin Processor Hardware Reference 8-47...
Page 326: Programming Examples
That is, the pulses are left aligned. Listing 8-2. Signal Generation // #define SINGLE_PULSE timer45_signal_generation: [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); #ifdef SINGLE_PULSE r7.l = PULSE_HI | PWM_OUT; #else 8-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 327 [--sp] = (r7:7, p5:5); p5.h = hi(IMASK); p5.l = lo(IMASK); /* register interrupt service routine */ r7.h = hi(isr_timer5); r7.l = lo(isr_timer5); [p5 + EVT12 - IMASK] = r7; /* unmask IVG12 in CEC */ ADSP-BF59x Blackfin Processor Hardware Reference 8-49...
Page 328 Unlike in a real application, the purpose of the interrupt service rou- tine shown in this example is just the clearing of the interrupt request and counting interrupt occurrences. Listing 8-4. Periodic Interrupt Requests // #define SINGLE_PULSE timer5_interrupt_generation: [--sp] = (r7:7, p5:5); 8-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 329 [--sp] = astat; [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_STATUS); p5.l = lo(TIMER_STATUS); r7.h = hi(TIMIL5); r7.l = lo(TIMIL5); [p5] = r7; r0+= 1; ssync; (r7:7, p5:5) = [sp++]; astat = [sp++]; rti; isr_timer5.end: ADSP-BF59x Blackfin Processor Hardware Reference 8-51...
Page 330 Enable TIMER5_PERIOD TIMER5_WIDTH P/2 - W/2 P/2 - W/2 TIMER4_PERIOD TIMER4_WIDTH P - W/2 P/2 - W-2 ENABLE IRQ1 IRQ2 IRQ3 TMR5 TMR4 P/2 - W/2 P - W/2 Figure 8-23. Non-Overlapping Clock Pulses 8-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 331 /* write values for initial period */ [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r0; [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r5; [p5 + TIMER5_PERIOD - TIMER_ENABLE] = r3; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r4; ADSP-BF59x Blackfin Processor Hardware Reference 8-53...
Page 332 = r7 - r5; CC = r7 < 0; if CC r7 = r6; [p5 + TIMER4_WIDTH - TIMER_ENABLE] = r7; /* disable after a certain number of periods */ r0+= -1; CC = r0 == 0; 8-54 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 333 [--sp] = (r7:7, p5:5); /* setup DAG2 */ r7.h = hi(buffReceive); r7.l = lo(buffReceive); i2 = r7; b2 = r7; l2 = length(buffReceive)*4; /* config timer for high pulses capture */ p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); ADSP-BF59x Blackfin Processor Hardware Reference 8-55...
Page 334: Unique Information For The Adsp-Bf59X Processor
Unique Information for the ADSP-BF59x Processor The ADSP-BF59x processor features one general-purpose timer module that contains three identical 32-bit timers. Each timer can be individually configured to operate in various modes. Although the timers operate com- 8-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 335: Interface Overview
Interface Overview Figure 8-24 shows the ADSP-BF59x specific block diagram of the gen- eral-purpose timer module. BLACKFIN SIC CONTROLLER GP TIMERS TIMER_STATUS TIMER_ENABLE TIMER_DISABLE PORT CONTROL Figure 8-24. Timer Block Diagram ADSP-BF59x Blackfin Processor Hardware Reference 8-57...
Page 336: External Interface
Timer 0 and timer 1 must not drive their TMRx pins. If operating in mode, the TMR0 TMR1 PWM_OUT OUT_DIS in the registers must be set. TIMER0_CONFIG TIMER1_CONFIG 8-58 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 337: Core Timer
“Unique Information for the ADSP-BF59x Processor” on page 9-9 Overview and Features The core timer is a programmable 32-bit interval timer which can gener- ate periodic interrupts. Unlike other peripherals, the core timer resides ADSP-BF59x Blackfin Processor Hardware Reference...
Page 338: Timer Overview
COUNT REGISTER LOAD LOGIC TIMER INTERRUPT TIMER ENABLE CCLK ZERO AND PRESCALE TCOUNT LOGIC Figure 9-1. Core Timer Block Diagram External Interfaces The core timer does not directly interact with any pins of the chip. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 339: Internal Interfaces
Interrupt Processing The timer’s dedicated interrupt request is a higher priority than requests from all other peripherals. The request goes directly to the core event controller (CEC) and does not pass through the system interrupt ADSP-BF59x Blackfin Processor Hardware Reference...
Page 340: Core Timer Registers
), the timer count register ( ), the timer TCNTL TCOUNT period register ( ), and the timer scale register ( ). As with all TPERIOD TSCALE core MMRs, these registers are always accessed by 32-bit read and write operations. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 341: Core Timer Control Register (Tcntl)
In auto reload mode the value written to may differ from the TCOUNT value to let the initial period be shorter or longer than following TPERIOD periods. To do this, write to first and overwrite afterward. TPERIOD TCOUNT ADSP-BF59x Blackfin Processor Hardware Reference...
Page 342: Core Timer Period Register (Tperiod)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined Period Value[31:16] 15 14 13 12 11 10 Period Value[15:0] Figure 9-4. Core Timer Period Register ADSP-BF59x Blackfin Processor Hardware Reference...
Page 343: Core Timer Scale Register (Tscale)
Listing 9-1. Core Timer Configuration #include <defBF527.h>/*ADSP-BF527 product is used as an example*/ .section L1_code; .global _main; _main: /* Register service routine at EVT6 and unmask interrupt */ p1.l = lo(IMASK); p1.h = hi(IMASK); ADSP-BF59x Blackfin Processor Hardware Reference...
Page 344 /* start in auto-reload mode */ r0 = TAUTORLD | TMPWR | TMREN (z); [p1] = r0; _main.forever: jump _main.forever; _main.end: /* interrupt service routine simple increments R6 */ isr_core_timer: [--sp] = astat; r6+= 1; astat = [sp++]; rti; isr_core_timer.end: ADSP-BF59x Blackfin Processor Hardware Reference...
Page 345: Unique Information For The Adsp-Bf59X Processor
Core Timer Unique Information for the ADSP-BF59x Processor None. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 346 Unique Information for the ADSP-BF59x Processor 9-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 347: 10 Watchdog Timer
The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by generating an event to the processor core if the watchdog expires before being updated by software. ADSP-BF59x Blackfin Processor Hardware Reference 10-1...
Page 348 The watchdog timer is often programmed to let the processor wake up from sleep mode after a programmable period of time.  For easier debugging, the watchdog timer does not decrement (even if enabled) when the processor is in emulation mode. 10-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 349: Interface Overview
Hardware ensures that those accesses are atomic. When the counter expires, one of three event requests can be generated. Either a reset or an NMI request is issued to the core event controller ADSP-BF59x Blackfin Processor Hardware Reference 10-3...
Page 350: Description Of Operation
0. Then, the programmed event is gener- ated. The counter stops decrementing and remains at zero. Additionally, latch bit in the register is set and can be interrogated by WDRO WDOG_CTL software in case event generation is not enabled. 10-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 351: Register Definitions
The register must always be accessed with 32-bit WDOG_CNT read/writes. A valid write to the register also preloads the watchdog counter. WDOG_CNT For added safety, the register can be updated only when the WDOG_CNT ADSP-BF59x Blackfin Processor Hardware Reference 10-5...
Page 352: Watchdog Status (Wdog_Stat) Register
WDOG_STAT WDOG_CNT  Enabling the watchdog timer does not automatically reload from WDOG_STAT WDOG_CNT register is a 32-bit unsigned system MMR that must be WDOG_STAT accessed with 32-bit reads and writes. 10-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 353: Watchdog Control (Wdog_Ctl) Register
This is a sticky bit that is WDRO WDOG_CTL set whenever the watchdog timer count reaches 0. It can be cleared only by writing a “1” to the bit when the watchdog has been disabled first. ADSP-BF59x Blackfin Processor Hardware Reference 10-7...
Page 354: Programming Examples
Listing 10-1. Watchdog Timer Configuration #include <defBF527.h>/*ADSP-BF527 product is used as an example*/ #define WDOGPERIOD 0x00200000 .section L1_code; .global _reset; _reset: /* optionally, test whether reset was caused by watchdog */ p0.h=hi(SWRST); p0.l=lo(SWRST); r6 = w[p0] (z); 10-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 355 Note that the value written to the register does WDOG_STAT not matter. Listing 10-2. Service Watchdog service_watchdog: [--sp] = p5; p5.h = hi(WDOG_STAT); p5.l = lo(WDOG_STAT); [p5] = r0; ADSP-BF59x Blackfin Processor Hardware Reference 10-9...
Page 356: Unique Information For The Adsp-Bf59X Processor
= [p5 + WDOG_CNT - WDOG_CTL]; [p5 + WDOG_CNT - WDOG_CTL] = r7; r7.l = WDEN | WDEV_GPI; w[p5] = r7; (p5:5, r7:7) = [sp++]; astat = [sp++]; rti; isr_watchdog.end: Unique Information for the ADSP-BF59x Processor None. 10-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 357: 11 Uart Port Controllers
UART behavior for the ADSP-BF59x that differs from the general infor- mation in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF59x Processor” on page 11-41 ADSP-BF59x Blackfin Processor Hardware Reference 11-1...
Page 358: Overview
The UART is logically compliant to EIA-232E, EIA-422, EIA-485 and LIN standards, but usually requires an external transceiver device to meet electrical requirements. In IrDA® (Infrared Data Association) mode, the UART meets the half-duplex IrDA SIR (9.6/115.2 Kbps rate) protocol. 11-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 359: Interface Overview
UART_SCR UART_MCR Figure 11-1. UART Block Diagram External Interface Each UART features an RX and a TX pin. These two pins usually connect to an external transceiver device that meets the electrical requirements of ADSP-BF59x Blackfin Processor Hardware Reference 11-3...
Page 360: Internal Interface
DAB bus A hardware-assisted autobaud detection mechanism is accomplished by coupling a specific GP Timer with a specific UART. For information on GP Timer - UART pairings for autobaud detection, see General-Purpose Ports chapter. 11-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 361: Description Of Operation
UART. On the receive side, the 16× clock is used to determine an IrDA pulse sample window, from which the RZI-modulated NRZ code is recovered. IrDA support is enabled by setting the bit in the register. IREN UART_GCTL The IrDA application requires external transceivers. ADSP-BF59x Blackfin Processor Hardware Reference 11-5...
Page 362: Uart Transmit Operation
DMA controller simply forwards it to the system interrupt controller (SIC). register and the internal register can be seen as a UART_THR two-stage transmit buffer. When data is pending in either one of these 11-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 363: Uart Receive Operation
The error handler routine may need to interrogate mul- tiple modules as to whether they requested the event. Error requests must be enabled by the bit in the register. The following error ELSI UART_IER ADSP-BF59x Blackfin Processor Hardware Reference 11-7...
Page 364: Irda Transmit Operation
UART clock periods. Similarly, the trailing edge of the pulse is truncated by eight UART clock periods. This results in the final representation of the original 0 as a high pulse of only 3 clock 11-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 365: Irda Receive Operation
Sources outside of the chip and not part of the transmitter can be avoided by appropriate shielding. The only other source of a glitch is the ADSP-BF59x Blackfin Processor Hardware Reference 11-9...
Page 366 0 transition corresponds to a UART NRZ value of 0. RECEIVED IrDA PULSE IR POL = 1 RECEIVED IrDA PULSE IR POL = 0 8/16 16/16 8/16 16/16 SAMPLING WINDOW PULSE DETECT OUTPUT RECOVERED NRZ INPUT Figure 11-4. IrDA Receiver Pulse Detection 11-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 367: Interrupt Processing
These writes also clear the TX interrupt request. How- UART_THR ever, they also initiate further transmission. If software doesn’t want to continue transmission, the TX request can alternatively be cleared by either clearing the bit or by reading the register. ETBEI UART_IIR ADSP-BF59x Blackfin Processor Hardware Reference 11-11...
Page 368: Bit Rate Generation
The divisor is split into the and the registers. UART_DLL UART_DLH These registers form a 16-bit divisor. The bit clock is divided by 16 so that: bit rate = /(16 × divisor) SCLK divisor = 65536 when UART_DLL UART_DLH 11-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 369: Autobaud Detection
For more information, see Chapter 7, “General-Purpose Ports”. The capture capabilities of the timers are often used to supervise the bit rate at runtime. If the Blackfin UART talks to a device supplied by a weak ADSP-BF59x Blackfin Processor Hardware Reference 11-13...
Page 370 11-5. STOP FRAME WIDTH Figure 11-5. Autobaud Detection Character 0x00 Because the example frame in Figure 11-5 encloses 8 data bits and 1 start bit, apply the formula: divisor = /(16 × 9) TIMER_WIDTH 11-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 371: Programming Model
In non-DMA mode, data is moved to and from the UART by the proces- sor core. To transmit a character, load it into . Received data can UART_THR be read from . The processor must write and read one character UART_RBR at time. ADSP-BF59x Blackfin Processor Hardware Reference 11-15...
Page 372 Interrupts also must be assigned and unmasked by the processor’s inter- rupt controller. The ISRs must clear the interrupt latches explicitly. See Figure 11-13 on page 11-29. 11-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 373: Dma Mode
If another DMA is started while data is still pending in the UART trans- mitter, there is no need to pulse the bit to initiate the second DMA. ETBEI If, however, the recent byte has already been loaded into the registers ADSP-BF59x Blackfin Processor Hardware Reference 11-17...
Page 374: Mixing Modes
UART_THR ter as soon as the bit permits. If the bit cannot be set, software THRE SYNC can poll the bit instead. DMA_RUN 11-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 375: Uart Registers
Table 11-2. UART Register Overview Address DLAB Operation Reset Function Name Offset Value Setting UART_RBR 0x0000 0x00 Receive buffer register UART_THR 0x0000 0x00 Transmit holding register UART_DLL 0x0000 0x01 Divisor latch low byte ADSP-BF59x Blackfin Processor Hardware Reference 11-19...
Page 376 0x000C X 0x00 Line control register UART_MCR 0x0010 0x00 Modem control register UART_LSR 0x0014 0x60 Line status register Read operations are destructive UART_SCR 0x001C X 0x00 Scratch register UART_GCTL 0x0024 0x00 Global control register 11-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 377: Uart Line Control (Uart_Lcr) Register
= 1 forces the transmit- ter to append one additional half bit, 1½ stop bits in total. Note that this bit does not impact data reception—the receiver is always satisfied with one stop bit. ADSP-BF59x Blackfin Processor Hardware Reference 11-21...
Page 378 0x57 1110 1010 0x60 0000 0110 0x57 1110 1010 If set, the bit forces the TX pin to low asynchronously, regardless of whether or not data is currently transmitted. It functions even when the 11-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 379: Uart Modem Control (Uart_Mcr) Register
LOOP_ENA (Loopback mode enable) Disconnects RX pin from RSR register Figure 11-8. UART Modem Control Registers Loopback mode disconnects the receiver’s input from the RX pin, but redirects it to the transmit output internally. ADSP-BF59x Blackfin Processor Hardware Reference 11-23...
Page 380: Uart Line Status (Uart_Lsr) Register
The bit cleared when UART_RBR register is read. UART_LSR bit indicates that the received parity bit does not match the expected value. The bit is set simultaneously with the bit. The 11-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 381: Uart Transmit Holding (Uart_Thr) Register
Because of the destructive nature of these read operations, special care should be taken. For more information, see the Memory chap- ter of the ADSP-BF59x Blackfin Processor Hardware Reference. bit indicates that the UART transmit channel is ready for new...
Page 382: Uart Receive Buffer (Uart_Rbr) Register
Setting this register without enabling system DMA causes the UART to notify the processor of data inventory state by means of interrupts. For proper operation in this mode, system interrupts must be enabled, and 11-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 383 The UART’s DMA is enabled by first setting up the system DMA control registers and then enabling the UART and/or interrupts in ERBFI ETBEI register. This is because the interrupt request lines double as UART_IER ADSP-BF59x Blackfin Processor Hardware Reference 11-27...
Page 384: Uart Interrupt Identification (Uart_Iir) Register
In the case where both interrupts are signaling, the reads 0x06. UART_IIR When a UART interrupt is pending, the interrupt service routine needs to clear the interrupt latch explicitly. Figure 11-13 shows how to clear any of the three latches. 11-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 385: Uart Divisor Latch (Uart_Dll And Uart_Dlh) Registers
 Because of the destructive nature of these read operations, special care should be taken. For more information, see the Memory chap- ter of the ADSP-BF59x Blackfin Processor Hardware Reference. UART Divisor Latch (UART_DLL and UART_DLH) Registers register is mapped to the same address as the...
Page 386: Uart Scratch (Uart_Scr) Register
UART hardware in any way. The contents are reset to 0x00. UART Scratch Register (UART_SCR) 15 14 13 12 11 10 Reset = 0x0000 Scratch[7:0] Figure 11-15. UART Scratch Register 11-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 387: Uart Global Control (Uart_Gctl) Register
The IrDA TX polarity change bit and the IrDA RX polarity change bit are effective only in IrDA mode. The two force error bits, , are intended for test purposes. They are useful for debugging software, espe- cially in loopback mode. ADSP-BF59x Blackfin Processor Hardware Reference 11-31...
Page 388: Programming Examples
/* clear DLAB again and config to */ w[p0+UART0_LCR-UART0_GCTL] = r7; /* 8 bits, no parity, 2 stop bits */ r7 = [sp++]; rts; uart_init.end: The subroutine in Listing 11-2 performs autobaud detection similarly to UART boot. 11-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 389 + TIMER_DISABLE - TIMER_STATUS] = r5; /* disable Timer x [p5 + TIMER_STATUS - TIMER_STATUS] = r6; /* clear pending latches */ /* period capture, falling edge to falling edge */ r7 = TIN_SEL | IRQ_ENA | PERIOD_CNT | WDTH_CAP (z); ADSP-BF59x Blackfin Processor Hardware Reference 11-33...
Page 390 TIMER4 is mapped to UART0 for this pur- pose. Note also that this example assumes the processor's UART0 pins are mapped to PORT G (PG7 and PG8). 11-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 391 Listing 11-4. UART Character Transmission /******************************************************* Transmit a single byte by polling the THRE bit. Input parameters: r0 holds the character to be transmitted p0 contains UART_GCTL register address Return values: none *******************************************************/ uart_putc: [--sp] = r7; uart_putc.wait: ADSP-BF59x Blackfin Processor Hardware Reference 11-35...
Page 392 [--sp] = rets; [--sp] = r0; uart_puts.loop: r0 = b[p1++] (z); CC = r0 == 0; if CC jump uart_puts.exit; call uart_putc; jump uart_puts.loop; uart_puts.exit: r0 = [sp++]; rets = [sp++]; rts; uart_puts.end: 11-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 393 In non-DMA interrupt operation, the three UART interrupt request lines may or may not be ORed together in the system interrupt controller. If they had three different service routines, they may look as shown in Listing 11-7. ADSP-BF59x Blackfin Processor Hardware Reference 11-37...
Page 394 /* clear TX interrupt enable */ bitclr(r7, bitpos(ETBEI)); /* ensure this sequence is not */ w[p0+UART0_IER-UART0_GCTL] = r7; /* interrupted by other IER accesses */ ssync; r7 = [sp++]; astat = [sp++]; rti; isr_uart_tx.end: 11-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 395 = [p1 + IMASK - IMASK]; /* unmask interrupt in CEC */ bitset(r0, bitpos(EVT_IVG10)); [p1] = r0; p1.l = lo(SIC_IMASK0); p1.h = hi(SIC_IMASK0); /* unmask interrupt in SIC */ /* (assume SIC_IMASK0 for this example)*/ r0.l = 0x0080; ADSP-BF59x Blackfin Processor Hardware Reference 11-39...
Page 396 = w[p5+DMA9_IRQ_STATUS-DMA9_CONFIG] (z); CC = bittst(r0,bitpos(DMA_RUN)); if CC jump wait4dma; p1.l=lo(sWorld); p1.h=hi(sWorld); call uart_puts; forever: jump forever; isr_uart_tx: [--sp] = astat; [--sp] = r7; r7 = DMA_DONE (z); /* W1C interrupt request */ 11-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 397: Unique Information For The Adsp-Bf59X Processor
UART Port Controllers w[p5+DMA9_IRQ_STATUS-DMA9_CONFIG] = r7; r7 = 0; /* pulse ETBEI for general case */ w[p0+UART0_IER-UART0_GCTL] = r7; ssync; r7 = [sp++]; astat = [sp++]; rti; isr_uart_tx.end: Unique Information for the ADSP-BF59x Processor None. ADSP-BF59x Blackfin Processor Hardware Reference 11-41...
Page 398 Unique Information for the ADSP-BF59x Processor 11-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 399: Two Wire Interface Controller
TWI behavior for the ADSP-BF59x that differs from the general informa- tion in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF59x Processor” on page 12-56. ADSP-BF59x Blackfin Processor Hardware Reference 12-1...
Page 400: Overview
• Master clock synchronization and support for clock low extension • Separate multiple-byte receive and transmit FIFOs • Low interrupt rate • Individual override control of data and clock lines in the event of bus lock-up 12-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 401: Interface Overview
TWI INTERFACE LOGIC CLOCK ADDRESS PRESCALER ARBITRATION COMPARE GENERATION Tx SHIFT REG Rx SHIFT REG 2-DEEP FIFO 2-DEEP FIFO Tx REG Rx REG Figure 12-1. TWI Block Diagram ADSP-BF59x Blackfin Processor Hardware Reference 12-3...
Page 402: External Interface
10 MHz. It is represented as a 7-bit binary value. Serial Data Signal (SDA) This is a bidirectional signal on which serial data is transmitted or received depending on the direction of the transfer. 12-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 403: Twi Pins
1 byte wide and data received can either be trans- ferred to the FIFO buffer or used in an address comparison. The address compare block supports address comparison in the event the TWI controller module is accessed as a slave. ADSP-BF59x Blackfin Processor Hardware Reference 12-5...
Page 404: Description Of Operation
TWI controller bit names. In this illustration, the TWI controller successfully transmits one byte of data. The slave has acknowl- edged both address and data. 12-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 405: Clock Generation And Synchronization
• Once the clock low count is complete, the serial clock line is three-stated and the clock synchronization logic enters into a delay mode (shaded area) until the line is detected at a logic 1 level. At this time the clock high count begins. ADSP-BF59x Blackfin Processor Hardware Reference 12-7...
Page 406: Bus Arbitration
1 level. The TWI controller generates and recognizes these transitions. Typically start and stop conditions occur at the beginning and at the conclusion of a transmission with the exception repeated start “combined” transfers, as shown in Figure 12-6. 12-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 407: General Call Support
(0x00) is indicated by the bit being set and GCALL by nature of the transfer the TWI controller is a slave-receiver. If the data associated with the transfer is to be NAK’ed, the bit can be set. ADSP-BF59x Blackfin Processor Hardware Reference 12-9...
Page 408: Fast Mode
Program the prescale value to the binary representation of f /10MHz SCLK All values should be rounded up to the next whole number. The TWI_ENA bit enable must be set. Note once the TWI controller is enabled a bus 12-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 409: Slave Mode
. Ultimately this prepares and enables slave TWI_SLAVE_CTL mode operation. As an example, programming the value 0x0005 enables slave mode operation, requires 7-bit addressing, and indi- cates that data in the transmit FIFO buffer is intended for slave mode transmission. ADSP-BF59x Blackfin Processor Hardware Reference 12-11...
Page 410: Master Mode Clock Setup
2. Program . This is the initial data TWI_XMT_DATA8 TWI_XMT_DATA16 transmitted. It is considered an error to complete the address phase of the transfer and not have data available in the transmit FIFO buffer. 12-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 411 Table 12-3. Master Mode Transmit Setup Interaction TWI Controller Master Processor Interrupt: XMTEMPTY – Transmit buffer is Write transmit FIFO buffer. empty. Acknowledge: Clear interrupt source bits. Interrupt: MCOMP – Master transfer com- Acknowledge: Clear interrupt source bits. plete. ADSP-BF59x Blackfin Processor Hardware Reference 12-13...
Page 412: Master Mode Receive
TWI Controller Master Processor Interrupt: RCVFULL – Receive buffer is full. Read receive FIFO buffer. Acknowledge: Clear interrupt source bits. Interrupt: MCOMP – Master transfer com- Acknowledge: Clear interrupt source bits. plete. Read receive FIFO buffer. 12-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 413: Repeated Start Condition
When read, would be zero. Set the bit to DCNT RSTART indicate a repeated start and set the bit if the following trans- MDIR fer will be a data receive. • interrupt MCOMP ADSP-BF59x Blackfin Processor Hardware Reference 12-15...
Page 414: Receive/Transmit Repeated Start Sequence
This interrupt is generated due to the arrival of a data byte in the receive FIFO. Set the bit to indicate a repeated start and RSTART clear the bit if the following transfer will be a data transmit. MDIR • interrupt MCOMP 12-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 415: Clock Stretching
During a master mode transmit, an interrupt is generated at the instant the transmit FIFO becomes empty. At this time, the most recent byte begins transmission. If the XMTSERV interrupt is not serviced, the con- cluding “acknowledge” phase of the transfer will be stretched. Stretching ADSP-BF59x Blackfin Processor Hardware Reference 12-17...
Page 416 TWI Controller Processor Interrupt: XMTSERV – Transmit FIFO buffer Acknowledge: Clear interrupt source bits. is empty. Write transmit FIFO buffer. Interrupt: MCOMP – Master transmit com- Acknowledge: Clear interrupt source bits. plete (DCNT= 0x00). 12-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 417: Clock Stretching During Fifo Overflow
Table 12-6. FIFO Overflow Case TWI Controller Processor Interrupt: RCVSERV – Receive FIFO buffer is Acknowledge: Clear interrupt source bits. full. Read receive FIFO buffer. Interrupt: MCOMP – Master receive complete. Acknowledge: Clear interrupt source bits. ADSP-BF59x Blackfin Processor Hardware Reference 12-19...
Page 418: Clock Stretching During Repeated Start Condition
(receive or transmit) is setup and activated. This sequence can be repeated as many times as required to string a series of repeated start transfers together. This is shown in Figure 12-11 and described in Table 12-7. 12-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 419 (receive), clearing RSTART, and setting new set. DCNT value (nonzero). Interrupt: RCVSERV – Receive FIFO is full. Acknowledge: Clear interrupt source bits. Read receive FIFO buffer. Interrupt: MCOMP – Master receive complete. Acknowledge: Clear interrupt source bits. ADSP-BF59x Blackfin Processor Hardware Reference 12-21...
Page 420: Programming Model
READ DATA FROM WRITE DATA INTO INTERRUPT TWI_XMT_DATA TWI_RCV_DATA SOURCE REGISTER REGISTER WRITE TWI_INT_STAT WRITE TWI_INT_STAT TO CLEAR INTERRUPT TO CLEAR INTERRUPT SCOMP WRITE TWI_INT_STAT TO CLEAR INTERRUPT DONE Figure 12-12. TWI Slave Mode 12-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 421 READ TWI_MASTER_STAT TO GET ERROR CAUSE TO CLEAR INTERRUPT HANDLE ERROR AS APPROPRIATE AND W1C THE CORRESPONDING BIT IN TWI_MASTER_STAT WRITE TWI_INT_STAT TO CLEAR MERR BIT WAIT FOR INTERRUPTS Figure 12-13. TWI Master Mode ADSP-BF59x Blackfin Processor Hardware Reference 12-23...
Page 422: Register Descriptions
) periods used in the generation of one internal time SCLK reference. The value of must be set to create an internal time ref- PRESCALE erence with a period of 10 MHz. It is represented as a 7-bit binary value. 12-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 423: Scl Clock Divider Register (Twi_Clkdiv)
CLKLOW CLKHI that add up to CLKLOW CLKHI CLKDIV field of the register specifies the number of 10 CLKHI TWI_CLKDIV MHz time reference periods the serial clock ( ) waits before a new clock ADSP-BF59x Blackfin Processor Hardware Reference 12-25...
Page 424: Twi Slave Mode Control Register (Twi_Slave_Ctl)
TWI Slave Mode Control Register (TWI_SLAVE_CTL) 15 14 13 12 11 10 Reset = 0x0000 SEN (Slave Enable) GEN (General Call Enable) STDVAL (Slave Transmit Data Valid) Figure 12-16. TWI Slave Mode Control Register 12-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 425 If cleared during a valid transfer, clock stretching ceases, the serial data line is released, and the current byte is not acknowledged. [1] The slave is enabled. Enabling slave and master modes of oper- ation concurrently is allowed. ADSP-BF59x Blackfin Processor Hardware Reference 12-27...
Page 426: Twi Slave Mode Address Register (Twi_Slave_Addr)
Gener- TWI_SLAVE_STAT ally slave mode status bits are not associated with the generation of interrupts. Master mode operation does not affect slave mode status bits. • General call ( GCALL 12-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 427: Twi Master Mode Control Register (Twi_Master_Ctl)
MEN (Master Mode Enable) SCLOVR (Serial Clock Override) MDIR (Master Transfer Direction) SDAOVR (Serial Data Override) FAST (Fast Mode) STOP (Issue Stop DCNT[7:0] (Data Condition) Transfer Count) RSTART (Repeat Start) Figure 12-19. TWI Master Mode Control Register ADSP-BF59x Blackfin Processor Hardware Reference 12-29...
Page 428 0xFF disables the counter. In this DCNT transfer mode, data continues to be transferred until it is concluded by setting the bit. STOP • Repeat start ( RSTART [0] Transfer concludes with a stop condition. 12-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 429 [0] Master mode functionality is disabled. If this bit is cleared dur- ing operation, the transfer is aborted and all logic associated with master mode transfers are reset. Serial data and serial clock (SDA, SCL) are no longer driven. Write-1-to-clear status bits are not affected. ADSP-BF59x Blackfin Processor Hardware Reference 12-31...
Page 430: Twi Master Mode Address Register (Twi_Master_Addr)
MDIR TWI Master Mode Address Register (TWI_MASTER_ADDR) 15 14 13 12 11 10 Reset = 0x0000 MADDR[6:0] (Master Mode Address) Figure 12-20. TWI Master Mode Address Register 12-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 431: Twi Master Mode Status Register (Twi_Master_Stat)
Upon a start condition, the setting of the register value is delayed due to the input filtering. Upon a stop condition the clearing of the register value occurs after t ADSP-BF59x Blackfin Processor Hardware Reference 12-33...
Page 432 [1] The current master transfer was aborted due to a receive buffer write error. The receive buffer and receive shift register were both full at the same time. This bit is W1C. 12-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 433 This bit is W1C. • Master transfer in progress ( MPROG [0] Currently no transfer is taking place. This can occur once a transfer is complete or while an enabled master is waiting for an idle bus. ADSP-BF59x Blackfin Processor Hardware Reference 12-35...
Page 434: Twi Fifo Control Register (Twi_Fifo_Ctl)
• Transmit buffer interrupt length ( XMTINTLEN This bit determines the rate at which transmit buffer interrupts are to be generated. Interrupts may be generated with each byte trans- mitted or after two bytes are transmitted. 12-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 435 This state is held XMTSTAT until this bit is cleared. During an active transmit the transmit buf- fer in this state responds as if the transmit buffer is empty. ADSP-BF59x Blackfin Processor Hardware Reference 12-37...
Page 436: Twi Fifo Status Register (Twi_Fifo_Stat)
FIFO buffer read using the peripheral data bus or write access by the receive shift register. Simultaneous accesses are allowed. [00] The FIFO is empty. [01] The FIFO contains one byte of data. A single byte peripheral read of the FIFO is allowed. [10] Reserved 12-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 437: Twi Interrupt Mask Register (Twi_Int_Mask)
TWI_INT_MASK output. Each mask bit corresponds with one interrupt source bit in the register. Reading and writing the register TWI_INT_STAT TWI_INT_MASK does not affect the contents of the register. TWI_INT_STAT ADSP-BF59x Blackfin Processor Hardware Reference 12-39...
Page 438: Twi Interrupt Status Register (Twi_Int_Stat)
Many of the bits serve as an indicator to further read and service various status registers. After servicing the interrupt source associated with a bit, the user must clear that interrupt source bit by writ- ing a 1 to it. 12-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 439 • Master transfer complete ( MCOMP [0] The completion of a transfer has not been detected. [1] The initiated master transfer has completed. In the absence of a repeat start, the bus has been released. ADSP-BF59x Blackfin Processor Hardware Reference 12-41...
Page 440 [0] A transfer is not in progress. An address match has not occurred since the last time this bit was cleared. [1] The slave has detected an address match and a transfer has been initiated. 12-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 441: Twi Fifo Transmit Data Single Byte
0 is the first byte to be transferred and byte 1 is the second byte to be transferred. With each access, the transmit status ( ) field in XMTSTAT register is updated. If an access is performed while the TWI_FIFO_STAT ADSP-BF59x Blackfin Processor Hardware Reference 12-43...
Page 442: Twi Fifo Receive Data Single Byte
) field in the RCVSTAT register is updated. If an access is performed while the TWI_FIFO_STAT FIFO buffer is empty, the data is unknown and the FIFO buffer status remains indicating it is empty. 12-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 443: Twi Fifo Receive Data Double Byte
FIFO buffer is not full, the read data is unknown and the existing FIFO buffer data and its status remains unchanged. RECEIVE DATA REGISTER TRANSMISSION LINE Figure 12-30. Receive Little Endian Byte Order ADSP-BF59x Blackfin Processor Hardware Reference 12-45...
Page 444: Programming Examples
0 and 0xFE (254). A value of 0xFF disables the counter ***********************************************************/ #define TWICount(x) (DCNT & ((x) << 6)) .section L1_data_b; .byte TX_file[file_size] = "DATA.hex"; .BYTE RX_CHECK[file_size]; .byte rcvFirstWord[2]; .SECTION program; 12-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 445 The address needs to be shifted one place to the right e.g., 1010 001x becomes 0101 0001 (0x51) the TWI controller will actually send out 1010 001x where x is either a 0 for writes or 1 for reads ADSP-BF59x Blackfin Processor Hardware Reference 12-47...
Page 446 R1 = R1 & R0; CC = R1 == R0; IF ! cc jump Rx_stat; R0 = W[P1 + LO(TWI_RCV_DATA16)](Z); /* Read data from the RX fifo ssync; /*********************************************************** check that master transfer has completed 12-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 447 5. Master Enable MEN. Setting this bit will kick off the transfer ***********************************************************/ R1 = TWICount(0xFE) | FAST | MEN; W[P1 + LO(TWI_MASTER_CTL)] = R1; SSYNC; /*********************************************************** loop to write data to a TWI slave device P3 times ***********************************************************/ ADSP-BF59x Blackfin Processor Hardware Reference 12-49...
Page 448: Slave Mode Setup
M_COMP1.END:W[P1 + LO(TWI_INT_STAT)] = R1; idle; _main.end: Slave Mode Setup Listing 12-2 shows how to configure the slave for interrupt based trans- fers. The interrupts are serviced in the subroutine shown in _TWI_ISR Listing 12-3. 12-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 449 R1 = TWI_ENA | 0xA (z); W[P1 + LO(TWI_CONTROL)] = R1; /*********************************************************** Slave address program the address to which this slave will respond to. this is an arbitrary 7-bit value ***********************************************************/ R1 = 0x5F; ADSP-BF59x Blackfin Processor Hardware Reference 12-51...
Page 450 TX FIFO can be used by this slave when a master requests data from it. 2. Slave Enable SEN to enable Slave functionality ***********************************************************/ R1 = STDVAL | SEN; W[P1 + LO(TWI_SLAVE_CTL)] = R1; TWI_SLAVE_INIT.END: P2.H = HI(TWI_RX); P2.L = LO(TWI_RX); 12-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 451 ENABLE TWI to generate interrupts at the core level ***********************************************************/ R1 = [P0 + LO(IMASK)]; BITSET(R1,BITPOS(EVT_IVG10)); [P0 + LO(IMASK)] = R1; /*********************************************************** wait for interrupts ***********************************************************/ idle; _main.END: Listing 12-3. TWI Slave Interrupt Service Routine /*********************************************************** ADSP-BF59x Blackfin Processor Hardware Reference 12-53...
Page 452 R0 = W[P1 + LO(TWI_RCV_DATA8)] (Z); /* read data */ B[P2++] = R0; /* store bytes into a buffer pointed to by P2 */ R0 = RCVSERV(Z); W[P1 + LO(TWI_INT_STAT)] = R0; /*clear interrupt source bit */ 12-54 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 453 /* exit */ /*********************************************************** slave overflow ***********************************************************/ SlaveOverflow: CC = BITTST(R1, BITPOS(SOVF)); if !CC JUMP SlaveTransferComplete; R0 = SOVF(Z); W[P1 + LO(TWI_INT_STAT)] = R0; /* clear interrupt source bit */ ssync; JUMP _TWI_ISR.END; /* exit */ ADSP-BF59x Blackfin Processor Hardware Reference 12-55...
Page 454: Electrical Specifications
/* store bytes into a buffer pointed to by P2 _TWI_ISR.END:RTI; Electrical Specifications All logic complies with the Electrical Specification outlined in the Philips C Bus Specification version 2.1 dated January 2000. Unique Information for the ADSP-BF59x Processor None. 12-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 455: Spi-Compatible Port Controller
Chapter A, “System Assignments”. SPI behavior for the ADSP-BF59x that differs from the general informa- tion in this chapter can be found in the section “Unique Information for the ADSP-BF59x Processor” on page 13-52. ADSP-BF59x Blackfin Processor Hardware Reference 13-1...
Page 456: Overview
• One SPI device select input and multiple chip select outputs • Programmable shift direction of MSB or LSB first • Interrupt generation on mode fault, overflow, and underflow • Shadow register to aid debugging 13-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 457: Interface Overview
(shifted serially out of the shift register) as new data is received (shifted serially into the other end of the same shift register). The synchronizes the shifting and sampling of the data on the two serial data pins. ADSP-BF59x Blackfin Processor Hardware Reference 13-3...
Page 458: External Interface
The number of active clock edges is equal to the number of bits driven on the data lines. Slave devices ignore the serial clock if the input is driven inactive (high). SPISS 13-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 459: Master-Out, Slave-In (Mosi) Signal
SPI device. The 8-bit host microcontroller is the SPI master.  The processor can be booted through its SPI interface to allow user application code and data to be downloaded before runtime. ADSP-BF59x Blackfin Processor Hardware Reference 13-5...
Page 460: Spi Slave Select Input Signal (Spiss)
SPI Slave Select Enable Output Signals When operating in master mode, Blackfin processors may use any GPIO pin to enable individual SPI slave devices by software. In addition, the SPI 13-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 461: Slave Select Inputs
When SPISS enabled as a master, can serve as an error detection input for the SPI SPISS in a multimaster environment. The bit in enables this PSSE SPI_CTL ADSP-BF59x Blackfin Processor Hardware Reference 13-7...
Page 462: Use Of Fls Bits In Spi_Flg For Multiple Slave Spi Systems
This feature may be available in EMISO some other microcontrollers. Therefore, it is possible to use the feature with any other SPI device that includes this EMISO functionality. 13-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 463 SPI DMA FIFO waiting to be transmitted. Therefore, software needs to poll in the register until SPI_STAT it goes low for two successive reads, at which point the SPI DMA ADSP-BF59x Blackfin Processor Hardware Reference 13-9...
Page 464: Internal Interfaces
SPI DMA FIFO waiting to be transmitted. Therefore, software needs to poll in the register until SPI_STAT it goes low for two successive reads, at which point the SPI DMA 13-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 465: Description Of Operation
CPHA = 0 CPHA = 1 MODE 0 MODE 1 SAMPLE DRIVE DRIVE SAMPLE EDGE EDGE EDGE EDGE MODE 2 MODE 3 SAMPLE DRIVE DRIVE SAMPLE EDGE EDGE EDGE EDGE Figure 13-5. SPI Modes of Operation ADSP-BF59x Blackfin Processor Hardware Reference 13-11...
Page 466 SPI_FLG Figure 13-6 shows the SPI transfer protocol for = 0. Note starts CPHA toggling in the middle of the data transfer, = 0, and = 0. SIZE LSBF 13-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 467 = 0, and = 0. SIZE LSBF (CPOL = 0) (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SPISS (TO SLAVE) (* = UNDEFINED) Figure 13-7. SPI Transfer Protocol for CPHA = 1 ADSP-BF59x Blackfin Processor Hardware Reference 13-13...
Page 468: Spi General Operation
During SPI data transfers, one SPI device acts as the SPI link master, where it controls the data flow by generating the SPI serial clock and asserting the SPI device select signal ( ). The other SPI device acts as SPISS 13-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 469: Clock Signals
The data is always shifted out on one edge of the MISO MOSI clock and sampled on the opposite edge of the clock. Clock polarity and ADSP-BF59x Blackfin Processor Hardware Reference 13-15...
Page 470: Interrupt Output
For more information about this interrupt output, see the discussion of bits in “SPI Control (SPI_CTL) Register” on page 13-35. TIMOD Functional Description The following sections describe the functional operation of the SPI. 13-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 471: Master Mode Operation (Non-Dma)
SPI_RDBR 7. With each new transfer initiate command, the SPI continues to send and receive words, according to the SPI transfer initiate mode. Figure 13-8 on page 13-29 for additional information. ADSP-BF59x Blackfin Processor Hardware Reference 13-17...
Page 472: Transfer Initiation From Master (Transfer Modes)
This is summarized in SPI_TDBR Table 13-1.  If the SPI port is enabled with = b#01 or = b#11, the TIMOD TIMOD hardware immediately issues a first interrupt or DMA request. 13-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 473: Slave Mode Operation (Non-Dma)
SPISS the active state (low), or by the first active edge of the clock ( ), depend- ing on the state of the bit in the register. CPHA SPI_CTL ADSP-BF59x Blackfin Processor Hardware Reference 13-19...
Page 474 MOSI register. If = 0 and the receive buffer is full, the incoming SPI_RDBR data is discarded, and the register is not updated. SPI_RDBR 13-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 475: Slave Ready For A Transfer
SPISS = 1, a transfer starts with the first active edge of for both CPHA slave and master devices. For a master device, a transfer is considered ADSP-BF59x Blackfin Processor Hardware Reference 13-21...
Page 476 If the SPI port is used to transmit and receive at the same time, or to switch between receive and transmit operation frequently, then the = b#00 mode may be the best operation option. In this mode, TIMOD 13-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 477: Master Mode Dma Operation
2. The processor core writes to the appropriate DMA registers to enable the SPI DMA channel and to configure the necessary work units, access direction, word count, and so on. For more informa- tion, see the Direct Memory Access chapter. ADSP-BF59x Blackfin Processor Hardware Reference 13-23...
Page 478 The DMA engine continues to read a word from the SPI DMA FIFO and writes to memory until the SPI DMA word count register transitions from “1” to “0”. The SPI continues receiving words until SPI DMA mode is disabled. 13-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 479 DMA data will be overwritten. Writes to the register during an active SPI receive DMA operation are SPI_TDBR allowed. Reads from the register are allowed at any time. SPI_RDBR ADSP-BF59x Blackfin Processor Hardware Reference 13-25...
Page 480: Slave Mode Dma Operation
4. If configured for receive, once the slave select input is active, the slave starts receiving and transmitting data on edges. The value in the shift register is loaded into the register at the end SPI_RDBR 13-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 481 If = 1 and the DMA FIFO is full, the SPI_CTL device continues to receive new data from the pin, overwriting the MOSI ADSP-BF59x Blackfin Processor Hardware Reference 13-27...
Page 482 = b#10), or when the DMA FIFO is not full (when = b#11). TIMOD TIMOD Error interrupts are generated when there is an overflow error condi- RBSY tion (when = b#10), or when there is a underflow error TIMOD condition (when = b#11). TIMOD 13-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 483 MSTR = 1 FLGx BITS TBDR WITH DATA TO SEND OVER SPI WRITE SPI_CTL TO DISABLE SPI PORT READ NEW DATA TIMOD = 01 FROM SPI_RDBR _RDBR TIMOD = 00 Figure 13-8. Core-Driven SPI Flow Chart ADSP-BF59x Blackfin Processor Hardware Reference 13-29...
Page 484 TO ADDRESS OF TO ADDRESS OF FIRST DESCRIPTOR FIRST DESCRIPTOR DMA7_CONFIG'S NDSIZE FIELD DETERMINES WHICH DMA REGISTERS TO INITIALIZE STATICALLY WRITE DMA REGISTERS: DMA7_START_ADDR DMA7_X_COUNT DMA7_X_MODIFY Figure 13-9. SPI DMA Flow Chart (Part 1 of 3) 13-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 485 WRITE SPI_FLG CPHA = 1 TO SELECT SLAVE(S) USING FLGx BITS MSTR = 1 WRITE DMA7_CONFIG TO ENABLE DMA WRITE SPI_CTL TO ENABLE SPI Figure 13-10. SPI DMA Flow Chart (Part 2 of 3) ADSP-BF59x Blackfin Processor Hardware Reference 13-31...
Page 486 WRITE SPI_FLG TO CPHA = 1 DESELECT SLAVE(S) VIA FLGx BITS MSTR = 1 WRITE SPI_CTL TO DISABLE SPI PORT WRITE DMA7_CONFIG TO DISABLE DMA Figure 13-11. SPI DMA Flow Chart (Part 3 of 3) 13-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 487: Spi Registers
SPI port When register is read, hardware events can be triggered receive data buffer SPI_SHADOW SPI port Register has the same contents as SPI_RDBR, but no data action is taken when it is read ADSP-BF59x Blackfin Processor Hardware Reference 13-33...
Page 488: Spi Baud Rate (Spi_Baud) Register
16.7 MHz 12.5 MHz 65,535 (0xFFFF) 131,070 763 Hz SPI Baud Rate Register (SPI_BAUD) 15 14 13 12 11 10 Reset = 0x0000 Baud Rate[15:0] SCLK/(2 × SPI_BAUD) Figure 13-12. SPI Baud Rate Register 13-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 489: Spi Control (Spi_Ctl) Register
MSTR MODF register is set. See “Mode Fault Error (MODF)” on SPI_STAT page 13-39. Figure 13-13 on page 13-36 provides the bit descriptions for SPI_CTL ADSP-BF59x Blackfin Processor Hardware Reference 13-35...
Page 490 0 - Disable SIZE (Size of Words) 1 - Enable 0 - 8 bits EMISO (Enable MISO) 1 - 16 bits 0 - MISO disabled 1 - MISO enabled Figure 13-13. SPI Control Register 13-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 491: Spi Flag (Spi_Flg) Register
, the port pin corresponding FLS1 SPI_FLG is driven as a slave select. SPISSEL1 If the bit is not set, the general-purpose port registers configure and FLSx control the corresponding port pins. ADSP-BF59x Blackfin Processor Hardware Reference 13-37...
Page 492: Spi Status (Spi_Stat) Register
These bits are set by hardware and must be cleared by software. To clear a sticky bit, the user must write a “1” to the desired bit position of . For example, if the bit is set, the user must write SPI_STAT 13-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 493: Mode Fault Error (Modf)
As soon as this error is detected, these actions occur: • The control bit in is cleared, configuring the SPI MSTR SPI_CTL interface as a slave • The control bit in is cleared, disabling the SPI system SPI_CTL ADSP-BF59x Blackfin Processor Hardware Reference 13-39...
Page 494: Transmission Error (Txe)
In this SPI_TDBR SPI_TDBR case, the contents of the transmission depend on the state of the bit in . The bit is sticky (W1C). SPI_CTL 13-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 495: Reception Error (Rbsy)
A write to is permitted in this mode, SPI_TDBR and this data is transmitted. If the control bit in the register is set, may be reset to SPI_CTL SPI_TDBR zero under certain circumstances. ADSP-BF59x Blackfin Processor Hardware Reference 13-41...
Page 496: Spi Receive Data Buffer (Spi_Rdbr) Register
SPI transfer may be initiated (if SPI_STAT = b#00). TIMOD SPI Receive Data Buffer Register (SPI_RDBR) Read Only 15 14 13 12 11 10 Reset = 0x0000 Receive Data Buffer[15:0] Figure 13-17. SPI Receive Data Buffer Register 13-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 497: Spi Rdbr Shadow (Spi_Shadow) Register
Core-Generated Transfer The following core-driven master-mode SPI example shows how to initial- ize the hardware, signal the start of a transfer, handle the interrupt and issue the next transfer, and generate a stop condition. ADSP-BF59x Blackfin Processor Hardware Reference 13-43...
Page 498: Initialization Sequence
= 1 : Active Low SCK * MSTR [12] = 1 : Device Is Master * WOM [13] = 0 : Normal MOSI/MISO Data Output (No Open Drain) * SPE [14] = 1 : SPI Module Is Enabled 13-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 499: Starting A Transfer
/* SPI Transmit Register */ P0.L = lo(SPI_TDBR); R0 = W[P1++] (z); /* Get First Data To Be Transmitted And Increment Pointer */ W[P0] = R0; /* Write to SPI_TDBR */ P0.H = hi(SPI_RDBR); ADSP-BF59x Blackfin Processor Hardware Reference 13-45...
Page 500: Post Transfer And Next Transfer
In order for a data transfer to end after the user has transferred all data, the following code can be used to stop the SPI. Note that this is typically done in the interrupt handler to ensure the final data has been sent in its entirety. 13-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 501: Dma-Based Transfer
/* Assume DMA7 as the channel for SPI DMA */ P0.H = hi(DMA7_CONFIG); P0.L = lo(DMA7_CONFIG); R0 = 0x1084(z); /* Autobuffer mode, IRQ on complete, linear 16-bit, mem read */ w[P0] = R0; P0.H = hi(DMA7_START_ADDR); P0.L = lo(DMA7_START_ADDR); ADSP-BF59x Blackfin Processor Hardware Reference 13-47...
Page 502: Spi Initialization Sequence
/* Enable slave-select output pin */ P1.H = hi(SPI_BAUD); P1.L = lo(SPI_BAUD); R0.L = 0x208E; /* Write to SPI baud rate register */ W[P0] = R0.L; ssync; /* If SCLK = 133MHz, SPI clock ~= 8kHz */ 13-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 503: Starting A Transfer
P1.L = lo(SPI_CTL); W[P1] = R1; ssync; Starting a Transfer After the initialization procedure in the given master mode, a transfer begins following enabling of SPI. However, the DMA must be enabled before enabling the SPI. ADSP-BF59x Blackfin Processor Hardware Reference 13-49...
Page 504: Stopping A Transfer
SPIF been shifted out. At that point, it is safe to shut down the SPI port and the DMA engine. 13-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 505 CC = R0 == 0; IF !CC JUMP Check_TXS; R2 = W[P0] (Z); /* Check if TXS stays clear for 2 reads */ R2 = R2 & R1; CC = R0 == 0; IF !CC JUMP Check_TXS; ADSP-BF59x Blackfin Processor Hardware Reference 13-51...
Page 506: Unique Information For The Adsp-Bf59X Processor
P0.L = lo(DMA7_CONFIG); P0.H = hi(DMA7_CONFIG); R0 = W[P0](Z); BITCLR (R0,0x0); /* Clear DMA enable bit */ W[P0] = R0; /* Disable DMA */ RTI; /* Exit Handler */ Unique Information for the ADSP-BF59x Processor None. 13-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 507: 14 Sport Controller
SPORT behavior for the ADSP-BF59x that differs from the general infor- mation in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF59x Processor” on page 14-73. ADSP-BF59x Blackfin Processor Hardware Reference 14-1...
Page 508: Overview
Many processors provide compati- ble interfaces, including processors from Analog Devices and other manufacturers. Each SPORT has its own set of control registers and data buffers.
Page 509 • Performs interrupt-driven, single word transfers to and from on-chip memory under processor control. ADSP-BF59x Blackfin Processor Hardware Reference 14-3...
Page 510: Interface Overview
MSB first or LSB first, synchronous to the serial clock on the TSCLK pin. The receive portion of the SPORT accepts data from the DRPRI DRSEC pin synchronous to the serial clock on the pin. When an entire word RSCLK 14-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 511 The data received on the primary and secondary signals is interleaved in main memory and can be retrieved by setting a stride in the data address generators (DAG) unit. For more information about ADSP-BF59x Blackfin Processor Hardware Reference 14-5...
Page 512 In addition to the serial clock signal, data must be signalled by a frame synchronization signal. The framing signal can occur either at the begin- ning of an individual word or at the beginning of a block of words. 14-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 513 2 Although shown as an external connection, the TSCLK1/RSCLK1 connection is internal in multi- channel mode. See “Multichannel Operation” on page 14-14. Figure 14-3 shows an example of a stereo serial device with three transmit and two receive channels connected to a processor with two SPORTs. ADSP-BF59x Blackfin Processor Hardware Reference 14-7...
Page 514: Sport Pin/Line Terminations
SPORTs. If connections on the data, clock, or frame sync lines are longer than six inches, consider using a series termination for strip lines on point-to-point connections. This may be necessary even when using low speed serial clocks, because of the edge rates. 14-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 515: Description Of Operation
A processor reset disables the SPORTs by clearing the SPORT_TCR1 , and registers (including the SPORT_TCR2 SPORT_RCR1 SPORT_RCR2 TSPEN enable bits) and the RSPEN SPORT_TCLKDIV SPORT_RCLKDIV , and clock and frame sync divisor registers. SPORT_TFSDIVx SPORT_RFSDIVx Any ongoing operations are aborted. ADSP-BF59x Blackfin Processor Hardware Reference 14-9...
Page 516: Setting Sport Modes
I2S format. To use these modes, set bits in the SPORT_RCR2 or SPORT_TCR2 registers. Setting RSFSE or TSFSE in SPORT_RCR2 or SPORT_TCR2 changes the operation of the frame sync pin to a left/right 14-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 517 , generating an edge. Transmission of the dummy word is not LRCLK required when the I S receiver is a Blackfin SPORT. Table 14-2. Stereo Serial Settings Bit Field Stereo Audio Serial Scheme Left-Justified DSP Mode RSFSE RRFST LARFS LRFS RFSR RCKFE ADSP-BF59x Blackfin Processor Hardware Reference 14-11...
Page 518 If the bit is set, the first word received or transmitted is a right channel. The default is to receive or transmit the left channel word first. 14-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 519 1 DSP mode does not identify channel. 2 TFS normally operates at f except for DSP mode which is 2 x f 3 TSCLK frequency is normally 64 x TFS but may be operated in burst mode. ADSP-BF59x Blackfin Processor Hardware Reference 14-13...
Page 520: Multichannel Operation
SPORT can receive and transmit data selectively from any of the 128 channels. These 128 channels can be any 128 out of the 1024 total channels. RX and TX must use the same 128-channel region to 14-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 521 SPORT_TX SPORT_RX When disabling the SPORT from multichannel operation, first disable and then disable . Note both must TXEN RXEN TXEN RXEN be disabled before re-enabling. Disabling only TX or RX is not allowed. ADSP-BF59x Blackfin Processor Hardware Reference 14-15...
Page 522 • Receive on channels 0 and 2, transmit on channels 1 and 2 • Multichannel frame delay is set to 1 “Timing Examples” on page 14-38 for more examples. MFD = 1 CHANNEL 0 CHANNEL 1 CHANNEL 2 RSCLK IGNORED Figure 14-6. Multichannel Operation 14-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 523: Multichannel Enable
Independent RDTYPE TDTYPE Independent RLSBIT TLSBIT Independent IRFS Independent ITFS Ignored RFSR TFSR Ignored DITFS Ignored LRFS LTFS Independent LARFS LATFS Both must be 0 RCKFE TCKFE Set or clear both to same value ADSP-BF59x Blackfin Processor Hardware Reference 14-17...
Page 524: Frame Syncs In Multichannel Mode
The SPORT’s data transmit pin is three-stated when the time slot is not active, and the signal serves as an 14-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 525: The Multichannel Frame
1 – 1024 channels, starting with channel 0. The particular channels of the multichannel frame that are selected for the SPORT are a combination of the window offset, the window size, and the multichannel select regis- ters. See Figure 14-7 on page 14-20. ADSP-BF59x Blackfin Processor Hardware Reference 14-19...
Page 526: Multichannel Frame Delay
The number of channels can be any value in the range of 0 to 15, corresponding to active window size of 8 to 128, in increments of 8; the default value of 0 corresponds to a minimum active 14-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 527: Window Offset
For example, a positive edge on causes data to be transmitted on the positive edge of the —either the same edge or the TSCLK following one, depending on when is set. LATFS ADSP-BF59x Blackfin Processor Hardware Reference 14-21...
Page 528: Channel Selection Register
For example, setting bit 7 in selects word 71 of the active window to be enabled. Setting MCS2 bit 2 in selects word 34 of the active window, and so on. MCS1 14-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 529: Multichannel Dma Data Packing
For example, if channels 1 and 10 are enabled, and the window size is 16, the DMA buffer size would have to be 16 words (unless the secondary side is enabled). The data to be ADSP-BF59x Blackfin Processor Hardware Reference 14-23...
Page 530: Support For H.100 Standard Protocol
MVIP-90 (2 Mbps data) and HMVIP (8 Mbps data), by recovering 2 MHz from 4 MHz or 8 MHz from the 16 MHz incoming clock with the proper phase relationship. A 2-bit mode signal ( in the MCCRM[1:0] 14-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 531: Functional Description
The second frame sync SPORT_TCLKDIV SPORT_RCLKDIV will cause the update. registers specify the number of SPORT_TFSDIV SPORT_RFSDIV transmit or receive clock cycles that are counted before generating a ADSP-BF59x Blackfin Processor Hardware Reference 14-25...
Page 532: Maximum Clock Rate Restrictions
Externally generated late transmit frame syncs also experience a delay from arrival to data output, and this can limit the maximum serial clock speed. See the ADSP-BF592 Blackfin Processor Data Sheet for exact timing specifications. 14-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 533: Word Length
Table 14-4 on page 14-28. These formats are applied to serial data words loaded into the SPORT_RX buffers. data words are not actually zero filled or SPORT_TX SPORT_TX sign extended, because only the significant bits are transmitted. ADSP-BF59x Blackfin Processor Hardware Reference 14-27...
Page 534: Companding
Lengths greater than 16 bits are not supported for companding operation. 14-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 535: Clock Signal Options
SPORT malfunction. See the ADSP-BF592 Blackfin Processor Data Sheet for details. The first internal frame sync will occur one frame sync delay after the SPORTs are ready. External frame syncs can occur as soon as the SPORT is ready. ADSP-BF59x Blackfin Processor Hardware Reference 14-29...
Page 536: Frame Sync Options
With frame syncs not required, interrupt or DMA requests may not be serviced frequently enough to guarantee continuous unframed data flow. Monitor status bits or check for a SPORT Error interrupt to detect underflow or overflow of data. 14-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 537: Internal Versus External Frame Syncs
Internal Versus External Frame Syncs Both transmit and receive frame syncs can be independently generated internally or can be input from an external source. The bits ITFS IRFS of the registers determine the frame sync SPORT_TCR1 SPORT_RCR1 source. ADSP-BF59x Blackfin Processor Hardware Reference 14-31...
Page 538: Active Low Versus Active High Frame Syncs
For the SPORT transmitter, setting = 1 in the register TCKFE SPORT_TCR1 selects the falling edge of to drive data and internally generated TSCLK frame syncs and selects the rising edge of to sample externally gener- TSCLK 14-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 539 DRIVE SAMPLE EDGE EDGE TSCLK = RSCLK INTERNAL OR EXTERNAL TFS = RFS INTERNAL OR EXTERNAL Figure 14-10. Example of = 0, Transmit and Receive Con- TCKFE RCKFE nected ADSP-BF59x Blackfin Processor Hardware Reference 14-33...
Page 540: Early Versus Late Frame Syncs (Normal Versus Alternate Timing)
Internally generated frame syncs are asserted for one clock cycle in early framing mode. Continuous operation is restricted to word sizes of 4 or ≥ 3). longer ( SLEN 14-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 541 = 0 or = 0) or LSB TLSBIT RLSBIT first ( = 1 or = 1). TLSBIT RLSBIT • Frame sync and clock are generated internally or externally. “Timing Examples” on page 14-38 for more examples. ADSP-BF59x Blackfin Processor Hardware Reference 14-35...
Page 542: Data Independent Transmit Frame Sync
Note that in this mode of operation, data is transmitted only at specified times. If the internally generated is used, a single write to the data SPORT_TX register is required to start the transfer. 14-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 543: Moving Data Between Sports And Memory
The SPORT error interrupt is asserted when any of the sticky status bits ) are set. The bits are cleared by ROVF RUVF TOVF TUVF ROVF RUVF writing 0 to . The bits are cleared by writing 0 to RSPEN TOVF TUVF TSPEN ADSP-BF59x Blackfin Processor Hardware Reference 14-37...
Page 544: Peripheral Bus Errors
These examples assume a word length of four bits ( = 3). Framing sig- SLEN nals are active high ( = 0 and = 0). LRFS LTFS Figure 14-13 on page 14-39 through Figure 14-18 on page 14-41 show framing for receiving data. 14-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 545 Note the output meets the input timing requirement; therefore, with two SPORT channels used, one SPORT channel could provide for the other SPORT channel. ADSP-BF59x Blackfin Processor Hardware Reference 14-39...
Page 546 (in normal mode) or RSCLK at the same time as the first bit (in alternate mode). This mode is appro- priate for multiword bursts (continuous reception). 14-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 547 Figure 14-21 on page 14-42 Figure 14-22 on page 14-43 show non-continuous and continuous transmission in the alternate framing mode. As noted previously for the receive timing dia- grams, the output meets the input timing requirement. ADSP-BF59x Blackfin Processor Hardware Reference 14-41...
Page 548 Figure 14-20. SPORT Continuous Transmit, Normal Framing TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 14-21. SPORT Transmit, Alternate Framing 14-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 549 DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 14-23. SPORT Transmit, Unframed Mode, Normal Framing TSCLK DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 14-24. SPORT Transmit, Unframed Mode, Alternate Framing ADSP-BF59x Blackfin Processor Hardware Reference 14-43...
Page 550: Sport Registers
Receive data register See description of FIFO buffering at “SPORT Receive Data (SPORT_RX) Register” on page 14-58 SPORT_STAT Receive and transmit status SPORT_MCM1 Primary multichannel mode Configure this register before configuration register enabling the SPORT 14-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 551: Register Writes And Effective Latency
Most configuration registers can only be changed while the SPORT is disabled ( = 0). Changes take effect after the TSPEN RSPEN SPORT is re-enabled. The only exceptions to this rule are the registers and multichannel select registers. TCLKDIV RCLKDIV ADSP-BF59x Blackfin Processor Hardware Reference 14-45...
Page 552: Sport Transmit Configuration (Sport_Tcr1 And Sport_Tcr2) Registers
). For example, SPORT_TCR1 TSPEN write (SPORT_TCR1, 0x0001) ; /* SPORT TX Enabled */ write (SPORT_TCR1, 0xFF01) ; /* ignored, no effect */ write (SPORT_TCR1, 0xFFF0) ; /* SPORT disabled, SPORT_TCR1 still equal to 0x0000 */ 14-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 553 TFSR (Transmit Frame Sync 1 - Data-independent TFS generated Required Select) 0 - Does not require TFS for every data word 1 - Requires TFS for every data word Figure 14-25. SPORT Transmit Configuration 1 Register ADSP-BF59x Blackfin Processor Hardware Reference 14-47...
Page 554 , and TSPEN TSCLK frame sync pins; it also shuts down the internal SPORT circuitry. In low power applications, battery life can be extended by clearing whenever the SPORT is not in use. TSPEN 14-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 555 SLEN  The frame sync signal is controlled by the SPORT_TFSDIV registers, not by . To produce a frame sync pulse SPORT_RFSDIV SLEN on each byte or word transmitted, the proper frame sync divider ADSP-BF59x Blackfin Processor Hardware Reference 14-49...
Page 556 SPORT from transmitting old data twice or transmitting garbled data if the processor is late in loading the register. SPORT_TX • Low transmit frame sync select. ( ). This bit selects an active LTFS (if set) or active high (if cleared). 14-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 557: Sport Receive Configuration (Sport_Rcr1 And Sport_Rcr2) Registers
A SPORT is enabled for receive if bit 0 ( ) of the receive configura- RSPEN tion 1 register is set to 1. This bit is cleared during either a hard reset or a soft reset, disabling all SPORT reception. ADSP-BF59x Blackfin Processor Hardware Reference 14-51...
Page 558 ). For example, SPORT_RCR1 RSPEN write (SPORT_RCR1, 0x0001) ; /* SPORT RX Enabled */ write (SPORT_RCR1, 0xFF01) ; /* ignored, no effect */ write (SPORT_RCR1, 0xFFF0) ; /* SPORT disabled, SPORT_RCR1 still equal to 0x0000 */ 14-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 559 SPORT to stop receiving data; it also RSPEN shuts down the internal SPORT receive circuitry. In low power applications, battery life can be extended by clearing when- RSPEN ever the SPORT is not in use. ADSP-BF59x Blackfin Processor Hardware Reference 14-53...
Page 560 (if set) or an external cleared). • Receive frame sync required select. ( ). This bit selects whether RFSR the SPORT requires (if set) or does not require (if cleared) a receive frame sync for every data word. 14-54 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 561: Data Word Formats
The format of the data words transferred over the SPORTs is configured by the combination of transmit and receive SLEN SLEN; RDTYPE TDTYPE ; and bits of the , and RLSBIT TLSBIT SPORT_TCR1 SPORT_TCR2 SPORT_RCR1 registers. SPORT_RCR2 ADSP-BF59x Blackfin Processor Hardware Reference 14-55...
Page 562 16-bit write. Use a 32-bit write for word length greater than 16 bits. When transmit is enabled, data from the FIFO is assembled in the TX Hold register based on , and then shifted into the primary TXSE SLEN 14-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 563: Sport Transmit Data (Sport_Tx) Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 Transmit Data[31:16] 15 14 13 12 11 10 Transmit Data[15:0] Figure 14-30. SPORT Transmit Data Register ADSP-BF59x Blackfin Processor Hardware Reference 14-57...
Page 564: Sport Receive Data (Sport_Rx) Register
2 WORDS OF W1 HIGH SECONDARY W0 HIGH PRIMARY SECONDARY DATA W0 LOW IN FIFO W0 LOW PRIMARY PRIMARY W0 HIGH W0 HIGH PRIMARY PRIMARY PAB/DAB PAB/DAB BUSES BUSES Figure 14-31. SPORT Receive FIFO Data Ordering 14-58 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 565 RX shift register and the RX hold register has not moved the data to the FIFO. The previously written word in the hold register is overwritten. The bit is a sticky bit; it is only cleared by disabling the ROVF SPORT RX. ADSP-BF59x Blackfin Processor Hardware Reference 14-59...
Page 566: Sport Status (Sport_Stat) Register
TX FIFO when it is full. TOVF It is a sticky W1C bit and is also cleared by writing = 0. Both TXEN are updated even when the SPORT is disabled. TOVF 14-60 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 567: Sport Transmit And Receive Serial Clock Divider (Sport_Tclkdiv And Sport_Rclkdiv) Registers
(as seen at the pin) and the value of the 16-bit serial SCLK clock divide modulus registers (the register, shown in SPORT_TCLKDIV Figure 14-34, and the register, shown in Figure 14-35 on SPORT_RCLKDIV page 14-62). ADSP-BF59x Blackfin Processor Hardware Reference 14-61...
Page 568: Sport Transmit And Receive Frame Sync Divider (Sport_Tfsdiv And Sport_Rfsdiv) Registers
The counting of serial clock cycles applies to either internally or externally generated serial clocks. These registers are shown in Figure 14-36 Figure 14-37 on page 14-63. 14-62 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 569: Sport Multichannel Configuration (Sport_Mcmc1 And Sport_Mcmc2) Registers
There are two multichannel configuration registers for each SPORT, shown in Figure 14-38 Figure 14-39 on page 14-64. These registers are used to configure the multichannel operation of the SPORT. The two control registers are shown below. ADSP-BF59x Blackfin Processor Hardware Reference 14-63...
Page 570: Sport Current Channel (Sport_Chnl) Register
CHNL[9:0] channel is serviced. The counter stops at the upper end of the defined win- dow. The channel select register restarts at 0 at each frame sync. As an 14-64 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 571: Sport Multichannel Receive Selection (Sport_Mrcsn) Registers
RX buffer. When the secondary receive side is enabled by the bit, both inputs are processed on enabled channels. RXSE ADSP-BF59x Blackfin Processor Hardware Reference 14-65...
Page 572: Sport Multichannel Transmit Selection (Sport_Mtcsn) Registers
For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on. Setting a particular bit in a register causes the SPORT to SPORT_MTCSn transmit the word in that channel’s position of the datastream. When the 14-66 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 573: Programming Examples
SPORTs, SPORT0 and SPORT1. The SPORT is usually employed for high-speed, continuous serial trans- fers. The example reflects this, in that the SPORT is set-up for auto-buffered, repeated DMA transfers. ADSP-BF59x Blackfin Processor Hardware Reference 14-67...
Page 574: Sport Initialization Sequence
65535) */ R1 = SPORT_TFSDIV_CONFIG; W[P0 + (SPORT0_TFSDIV - SPORT0_TCR1)] = R1; /* TFSDIV register */ /* Transmit configuration */ /* Configuration register 2 (for instance 0x000E for 16-bit wordlength) */ R1 = SPORT_TRANSMIT_CONF_2; 14-68 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 575 /* Configuration register 1 (for instance 0x4410 for external clk and framesync) */ R1 = SPORT_RECEIVE_CONF_1; W[P0] = R1; ssync; /* NOTE: SPORT0 RX NOT enabled yet (bit 0 of RCR1 must be zero) */ ADSP-BF59x Blackfin Processor Hardware Reference 14-69...
Page 576: Dma Initialization Sequence
R1 = (length(rx_buf)/4)(z); W[P0 + (DMA3_X_COUNT - DMA3_CONFIG)] = R1; /* X_count register */ R1 = 4(z); /* 4 bytes in a 32-bit transfer */ W[P0 + (DMA3_X_MODIFY - DMA3_CONFIG)] = R1; /* X_modify register */ 14-70 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 577 W[P0 + (DMA4_X_MODIFY - DMA4_CONFIG)] = R1; /* X_modify register */ /* start_address register points to memory buffer to be transmitted from */ R1.l = tx_buf; R1.h = tx_buf; [P0 + (DMA4_START_ADDR - DMA4_CONFIG)] = R1; ADSP-BF59x Blackfin Processor Hardware Reference 14-71...
Page 578: Interrupt Servicing
[--SP] = RETI; /* nesting of interrupts */ /* clear DMA interrupt request */ P0.h = hi(DMA4_IRQ_STATUS); P0.l = lo(DMA4_IRQ_STATUS); = 1; W[P0] = R1.l; /* write one to clear */ RETI = [SP++]; rti; 14-72 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 579: Starting A Transfer
/* dummy wait loop (do nothing but waiting for interrupts) */ wait_forever: jump wait_forever; Unique Information for the ADSP-BF59x Processor This section describes Clock Gating Functionality Modes of Opera- tion that are unique to the ADSP-BF59x processors. ADSP-BF59x Blackfin Processor Hardware Reference 14-73...
Page 580: Clock Gating Functionality
Key requirements of the converter are that the digital pins remain quiet during critical times of the conversion process. In order to meet this requirement must be active only when necessary to read conversion 14-74 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 581: Modes Of Operation
The timers are simultaneously enabled via the TIMER_ENABLE register to ensure that the edges are perfectly synchronized. As in Gated Clock Mode 0, the signal is looped back to to allow correct ADSP-BF59x Blackfin Processor Hardware Reference 14-75...
Page 582: Programming Model
ADSP-BF59x to AD71090 inter- face with a 25 MHz data clock and conversion rate of approximately 390 kSPS. In this example, the SPORT is connected in ADC Interface Mode 0. 14-76 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 583 TFSDIV • = 16 bits SLEN • = 1 (falling edge drive) TCKFE • = 0 (sample on falling edge) RCKFE • = 1 (late frame sync) LATFS • = 1 (active low LTFS ADSP-BF59x Blackfin Processor Hardware Reference 14-77...
Page 584 Internal TFS Internal RFS (= 680 ns) C12 C11 C7 C6 C5 C4 C1 C0 D14 D13 D9 D8 D7 D6 D3 D2 D1 D0 Figure 14-44. ADSP-BF59x to AD71090 Interface Timing (@ 25 MHz) 14-78 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 585: Parallel Peripheral Interface
Chapter A, “System Assignments”. PPI behavior for the ADSP-BF59x that differs from the general informa- tion in this chapter can be found in the section “Unique Information for the ADSP-BF59x Processor” on page 15-37 ADSP-BF59x Blackfin Processor Hardware Reference 15-1...
Page 586: Overview
• Interrupt generation on overflow and underrun Typical peripheral devices that can be interfaced to the PPI port: • A/D converters • D/A converters • LCD panels • CMOS sensors • Video encoders • Video decoders 15-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 587: Interface Overview
GP Timers to work synchronously with the PPI. Depending on PPI operation mode, the can either equal or invert the PPI_CLK TMRCLK input. For more information, see Chapter 8, “General-Purpose Timers”. ADSP-BF59x Blackfin Processor Hardware Reference 15-3...
Page 588: Description Of Operation
TX mode, 0 frame 0 or 1 0 or syncs TX mode, 1 inter- 0 or 1 0 or nal or external frame sync TX mode, 2 exter- 0 or 1 0 or nal frame syncs 15-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 589: Functional Description
The start of active video (SAV) and end of active video (EAV) signals indicate the beginning and end of data elements to read in on each line. SAV occurs on a 1-to-0 transition of , and EAV begins on a ADSP-BF59x Blackfin Processor Hardware Reference 15-5...
Page 590 HORIZONTAL CODE CODE BLANKING (H = 1) (H = 0) DIGITAL VIDEO STREAM 268 (280 FOR PAL) 1440 1716 (1728 FOR PAL) Figure 15-2. ITU-R 656 8-Bit Parallel Data Stream for NTSC (PAL) Systems 15-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 591 EAV sequences (that is, transition from = 0 to = 1). The bit definitions are as follows: • = 0 for field 1 • = 1 for field 2 ADSP-BF59x Blackfin Processor Hardware Reference 15-7...
Page 592 Table 15-2. Control Byte Sequences for 8-bit and 10-bit ITU-R 656 Video 8-bit Data 10-bit Data (MSB) Preamble Control Byte 15-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 593: Itu-R 656 Input Modes
In this mode, the entire incoming bitstream is read in through the PPI. This includes active video as well as control byte sequences and ancillary data that may be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization to field 1 occurs, ADSP-BF59x Blackfin Processor Hardware Reference 15-9...
Page 594: Active Video Only
VBI. Control byte sequence information is always logged. The user specifies the number of total lines (active plus vertical blanking) per frame in the MMR. PPI_FRAME 15-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 595: Itu-R 656 Output Mode
The user pro- grams this MMR for the number of lines expected in each frame of video, and the PPI keeps track of the number of EAV-to-SAV transitions that ADSP-BF59x Blackfin Processor Hardware Reference 15-11...
Page 596: General-Purpose Ppi Modes
RX mode, 2 or 3 internal frame syncs Output Output Output (if Input used) TX mode, 0 frame syncs Not used Not used Not used Output TX mode, 1 external frame sync Input Not used Not used Output 15-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 597 PPI_FS1 samples have been transferred out, the sync has priority PPI_COUNT and starts a new line transfer sequence. This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process. ADSP-BF59x Blackfin Processor Hardware Reference 15-13...
Page 598: Data Input (Rx) Modes
PPI_CONTROL • External trigger: An external source sends a single frame sync (tied ) at the start of the transaction, when = 0 and PPI_FS1 FLD_SEL = b#11. PORT_CFG 15-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 599: 1, 2, Or 3 External Frame Syncs
CONVERTER PPI_FS1 FRAMESYNC PPIx 8–16 BITS DATA DATA PPI_CLK VIDEO SOURCE PPI_FS1 HSYNC PPI_FS2 VSYNC PPI_FS3 FIELD DATA 8–16 BITS DATA PPIx PPI_CLK Figure 15-7. RX Mode, External Frame Syncs ADSP-BF59x Blackfin Processor Hardware Reference 15-15...
Page 600: Or 3 Internal Frame Syncs
The PPI supports several modes for data output. These modes differ chiefly by the way the data is framed. Refer to Table 15-1 on page 15-4 for information on how to configure the PPI for each mode. 15-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 601: No Frame Syncs
 There is a mandatory delay of 1.5 cycles, plus the value PPI_CLK programmed in , between assertion of the external frame PPI_DELAY sync(s) and the transfer of valid data out through the PPI. ADSP-BF59x Blackfin Processor Hardware Reference 15-17...
Page 602: 1, 2, Or 3 Internal Frame Syncs
The 3-sync mode is useful for connecting to video and graphics displays, as shown in the bottom part of Figure 15-11. A 2-sync mode is implicitly supported by leaving unconnected in this case. PPI_FS3 15-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 603: Frame Synchronization In Gp Modes
PWM operation). If is not used in the configured PPI_FS2 PPI mode, its corresponding timer operates as it normally would, unre- stricted in functionality. The state of depends completely on the PPI_FS3 ADSP-BF59x Blackfin Processor Hardware Reference 15-19...
Page 604: Modes With External Frame Syncs
In such modes the timers associated with pins can still be used for a purpose not involving PPI_FS1 PPI_FS2 the actual pin. However, timer access to a pin is disabled when the TMRx 15-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 605: Programming Model
PPI operation in this mode. For more information, see the Gen- eral-Purpose Timers chapter. Programming Model The following sections describe the PPI programming model. ADSP-BF59x Blackfin Processor Hardware Reference 15-21...
Page 606: Dma Operation
DMA_CONFIG for the entire frame. • Setting = 320, = 240, and = 0 interrupts XCOUNT YCOUNT DI_SEL only on the completion of the frame (when 240 rows of 320 bytes have been transferred). 15-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 607 PPI frame TIMER_ENABLE syncs. Figure 15-12 shows a flow diagram detailing the steps on how to config- ure the PPI for the various modes of operation. ADSP-BF59x Blackfin Processor Hardware Reference 15-23...
Page 608 PROGRAM TIMER(S) EXTERNAL INTERNAL FS? LINKED WITH FS TRIGGER? PROGRAM PPI_FRAME PROGRAM PPI_COUNT WRITE DMA_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI WRITE TIMER_ENABLE TO ENABLE TIMERS INTERNAL FS? Figure 15-12. PPI Flow Diagram 15-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 609: Ppi Registers
SKIP_EN being read in through the PPI. By ignoring data elements, the PPI is able to conserve DMA bandwidth. ADSP-BF59x Blackfin Processor Hardware Reference 15-25...
Page 610 0 - Field 1 1 - Fields 1 and 2 In RX mode with external frame sync, when PORT_CFG = 11: 0 - External trigger 1 - Internal trigger Figure 15-13. PPI Control Register 15-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 611 Consider this data transported into the PPI via DMA: 0xCE, 0xFA, 0xFE, 0xCA..• With set: PACK_EN This is read into the PPI, configured for an 8-bit port width: 0xCE, 0xFA, 0xFE, 0xCA... This is transferred onto the DMA bus: 0xFACE, 0xCAFE,... ADSP-BF59x Blackfin Processor Hardware Reference 15-27...
Page 612 (note LSBs are transferred first): 0xCE, 0xFA, 0xFE, 0xCA,... • With cleared: PACK_EN This is DMAed to the PPI: 0xFACE, 0xCAFE,... This is transferred out through the PPI, configured for an 8-bit port width: 0xCE, 0xFE,... 15-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 613: Ppi Status Register (Ppi_Status)
ITU-R 656 control word preamble. The bit is valid only in ITU-R 656 modes. If = 1, an error was detected in the preamble. ERR_DET = 0, no error was detected in the preamble. ERR_DET ADSP-BF59x Blackfin Processor Hardware Reference 15-29...
Page 614 In this condition, the programmed number of lines per frame in does not match up with the “frame start detect” con- PPI_FRAME dition (see the information note on page 15-34). A frame track error 15-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 615 This flag does not apply for non ITU-R 656 modes; in this case, once the value in is reached, the PPI simply stops PPI_COUNT counting until receiving the next frame sync. PPI_FS1 ADSP-BF59x Blackfin Processor Hardware Reference 15-31...
Page 616: Ppi Delay Count Register (Ppi_Delay)
Thus, at the beginning of a new line of data, there is no need to rewrite the value of this register. For example, to receive or transmit 100 samples through the PPI, set to 99. PPI_COUNT 15-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 617: Ppi Lines Per Frame Register (Ppi_Frame)
If the start of a new frame (or field, for ITU-R 656 mode) is detected before the number of lines specified by have been transferred, a PPI_FRAME frame track error results, and the bit in is set. FT_ERR PPI_STATUS ADSP-BF59x Blackfin Processor Hardware Reference 15-33...
Page 618: Programming Examples
Programming Examples The PPI can be configured to receive data from a video source in several RX modes. The following programming examples (Listing 15-1 through Listing 15-5) describe the ITU-R 656 entire field input mode. 15-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 619 W[P0] = R0.L; /* DMA0_X_COUNT */ R0.L = 256; P0.L = lo(DMA0_X_COUNT); P0.H = hi(DMA0_X_COUNT); W[P0] = R0.L; /* DMA0_X_MODIFY */ R0.L = 0x0001; P0.L = lo(DMA0_X_MODIFY); P0.H = hi(DMA0_X_MODIFY); W[P0] = R0.L; ssync; config_dma.END: RTS; ADSP-BF59x Blackfin Processor Hardware Reference 15-35...
Page 620 P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); R0.L = W[P0]; bitset(R0,0); W[P0] = R0.L; ssync; Listing 15-4. Enable PPI /* PPI_CONTROL */ P0.L = lo(PPI_CONTROL); P0.H = hi(PPI_CONTROL); R0.L = W[P0]; bitset(R0,0); W[P0] = R0.L; ssync; 15-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 621: Unique Information For The Adsp-Bf59X Processor
Parallel Peripheral Interface Listing 15-5. Clear DMA Completion Interrupt /* DMA0_IRQ_STATUS */ P2.L = lo(DMA0_IRQ_STATUS); P2.H = hi(DMA0_IRQ_STATUS); R2.L = W[P2]; BITSET(R2,0); W[P2] = R2.L; ssync; Unique Information for the ADSP-BF59x Processor None. ADSP-BF59x Blackfin Processor Hardware Reference 15-37...
Page 622 Unique Information for the ADSP-BF59x Processor 15-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 623: System Reset And Booting
The boot kernel processes the boot stream block-by-block until it is instructed by a special command to terminate the procedure and jump to the application’s programmable start address, which traditionally is at 0xFFA0 0000 in on-chip L1 memory. This process is called “booting.” ADSP-BF59x Blackfin Processor Hardware Reference 16-1...
Page 624 Boot from internal L1 ROM In this mode, the processor starts instruction execu- (full user control) tion at the base address of on-chip L1 instruction ROM, entirely bypassing the boot ROM. 16-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 625: Reset And Power-Up
Sleep or Deep Sleep modes.) or the register can be SWRST SYSCR read to determine whether the reset source was the watchdog timer. ADSP-BF59x Blackfin Processor Hardware Reference 16-3...
Page 626: Hardware Reset
GND. The pins and the corresponding DDEXT bits in the register configure the boot mode that is employed after SYSCR hardware reset or system software reset. See the Blackfin Processor Program- ming Reference for further information. 16-4 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 627: Software Resets
DBGCTL through the JTAG port. A software reset only affects the state of the core. The boot kernel immedi- ately issues a system reset to keep consistency with the system domain. ADSP-BF59x Blackfin Processor Hardware Reference 16-5...
Page 628: Reset Vector
For a programming example, see “System Reset” on page 16-71. Listing 16-1 Listing 16-2 on page 16-72 show code examples that handle the reset event. See the Blackfin Processor Programming Reference for details on user and supervisor modes. 16-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 629 Systems that do not work in an operating system environment may not enter user mode. Typically, the interrupt level needs to be degraded down to IVG15. Listing 16-3 Listing 16-4 on page 16-73 show how this is accomplished. ADSP-BF59x Blackfin Processor Hardware Reference 16-7...
Page 630: Basic Booting Process
In host boot scenarios, the non-volatile memory more likely connects to the host processor rather than directly to the Blackfin processor. After reset, the headers are read and parsed by the 16-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 631 The entire source code of the boot ROM is shipped with the VisualDSP++ tools installation. Refer to the source code for any addi- tional questions not covered in this manual. Note that minor maintenance ADSP-BF59x Blackfin Processor Hardware Reference 16-9...
Page 632: Block Headers
Figure 16-4 on page 16-11. The 16 bytes of the block header are functionally grouped into four 32-bit words, the , the , the , and the BLOCK CODE TARGET ADDRESS BYTE COUNT fields. ARGUMENT 16-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 633 BLOCK 0 HEADER BLOCK 0 PAYLOAD OFFSET 0X0000 BLOCK CODE BLOCK 1 HEADER OFFSET 0X0004 TARGET ADDRESS OFFSET 0X0008 BYTE COUNT BLOCK 2 HEADER OFFSET 0X000C ARGUMENT BLOCK 2 PAYLOAD Figure 16-4. Boot Stream Headers ADSP-BF59x Blackfin Processor Hardware Reference 16-11...
Page 634: Block Code
8-bit, 16-bit or 32-bit DMA and how to program the source modifier of a memory DMA. Particularly in case of memory boot modes, this field is interrogated by the boot kernel to differentiate the 8-bit, 16-bit, and 32-bit cases. 16-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 635 Default 128-bit boot from 128-bit source 1 Reserved to differentiate from ADSP-BF53x boot streams. 2 Used by all byte-wise serial boot modes. 3 Not supported by ADSP-BF59x Blackfin products. 4 Applicable only to memory boot modes. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 636: Block Flags Field
It may or may not be overwritten by application data later in the boot process. If the code is loaded earlier or resides in ROM, the init block can be zero sized (no payload). 16-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 637: Header Checksum Field
31 bytes in the boot block header. The boot kernel jumps to the error routine if the result of an XOR operation across all 32 header bytes (including the value) differs from zero. The default error routine is HDRCHK ADSP-BF59x Blackfin Processor Hardware Reference 16-15...
Page 638: Target Address
BFLAG_INDIRECT bit is processed. By default the address range BFLAG_INDIRECT 0xFF80 7F00–0xFF80 7FEF is used for intermediate storage. 16-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 639: Byte Count
When the CRC32 feature is acti- vated, the field holds the checksum over the payload of the ARGUMENT block. ADSP-BF59x Blackfin Processor Hardware Reference 16-17...
Page 640: Boot Host Wait (Hwait) Feedback Strobe
The signal is not released until the boot kernel is ready for data, or when a receive DMA is started. As soon as the DMA completes, becomes HWAIT active again. 16-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 641: Boot Termination
After the successful download of the application into the bootable mem- ory, the boot kernel passes control to the user application. By default this is performed by jumping to the vector stored in the register. The EVT1 ADSP-BF59x Blackfin Processor Hardware Reference 16-19...
Page 642: Single Block Boot Streams
Table 16-5. Header for a Single Block Boot Stream Field Value Comments BLOCK CODE 0xAD33 C001 0xAD00 0000 | XORSUM | BFLAG_FINAL | BFLAG_FIRST | (DMACODE & 0x1) TARGET ADDRESS 0xFFA0 0000 Start address of block and application code 16-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 643: Advanced Boot Techniques
BFLAG_INIT CALL get address of the block. On ADSP-BF59x Blackfin processors, initcode routines follow the C language calling convention so they can be coded in C language or assembly. The expected prototype is: void initcode(ADI_BOOT_DATA* pBootStruct)
Page 644 Sometimes initcode boot blocks have no payload and the field BYTE COUNT is set to zero. Then the only purpose of the block may be to instruct the boot kernel to issue the instruction. CALL 16-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 645 1. Boot initcode into L1 memory. 2. Execute initcode. 3. Overwrite initcode with final application code. 4. Boot data/code into memory. 5. Continue program execution with block n. ADSP-BF59x Blackfin Processor Hardware Reference 16-23...
Page 646 Initcodes provide only a callable sub-function, so they look more like a library than an application. Nevertheless, unlike library files ( file extension), the symbol addresses have already been .DLB resolved by the linker. 16-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 647: Quick Boot
• The bit in the word of the BFLAG_WAKEUP dFlag ADI_BOOT_DATA structure indicates that the final decision was to perform a quick boot. If the boot kernel is called from the application, then the ADSP-BF59x Blackfin Processor Hardware Reference 16-25...
Page 648: Indirect Booting
• In some advanced booting scenarios, the core needs to access the boot data during the booting process, for example in processing decompression, decryption and checksum algorithms at boot time. 16-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 649: Callback Routines
BFLAG_CALLBACK The purpose of the callback routine is to apply standard processing to the block data. Typically, callback routines contain checksum, decryption, ADSP-BF59x Blackfin Processor Hardware Reference 16-27...
Page 650 Callback routines meet C language calling conventions for subroutines. The prototype is as follows. s32 CallBackFunction (ADI_BOOT_DATA* pBootStruct, ADI_BOOT_BUFFER* pCallbackStruct, s32 dCbFlags); The VisualDSP++ header file defines the type ADI_BOOT_CALLBACK_FUNC the following way: typedef s32 ADI_BOOT_CALLBACK_FUNC (ADI_BOOT_DATA*, ADI_BOOT_BUFFER*, s32 ) ; 16-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 651 A callback routine also has a boolean return parameter in register . If the return value is non-zero, the subsequent memory DMA does not execute. When the flag is set, the return value has no effect. CBFLAG_DIRECT ADSP-BF59x Blackfin Processor Hardware Reference 16-29...
Page 652: Error Handler
CRC Checksum Calculation The ADSP-BF59x Blackfin processors provide an initcode and a callback routine in ROM that can be used for CRC32 checksum generation during boot time. The checksum routine only verifies the payload data of the blocks.
Page 653 In slave boot modes, the boot kernel uses the address of the dArgument field in the block as the destination for the required dummy pHeader DMAs when payload data is consumed from blocks. If the BFLAG_IGNORE ADSP-BF59x Blackfin Processor Hardware Reference 16-31...
Page 654: Calling The Boot Kernel At Runtime
HWAIT the progress of the boot process. However, by using the emulator, there are many possibilities for debug- ging the boot process. The entire source code of the boot kernel is 16-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 655 If BFLAG_INIT set, the initcode can be debugged. _bootrom.bootkernel.exit Once the boot kernel arrives at the _bootrom.bootkernel exit label, it detects a flag. After some house- BFLAG_FINAL keeping, it jumps to the vector. EVT1 ADSP-BF59x Blackfin Processor Hardware Reference 16-33...
Page 656 Most of the data structures used by the boot kernel reside on the stack in scratchpad memory. While executing the boot kernel routine (excluding subroutines), the points to the structure. Type ADI_BOOT_DATA “ ” in the VisualDSP++ expression window to see (ADI_BOOT_DATA*) $P5 the structure content. 16-34 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 657: Boot Management
, which is discussed in “SPI Master BFROM_SPIBOOT Boot Modes” on page 16-40. The user application, the boot manager application, or an initcode can call these functions to load the requested boot data. Using the BFLAG_RETURN ADSP-BF59x Blackfin Processor Hardware Reference 16-35...
Page 658: Multi-Dxe Boot Streams
Figure 16-7 on page 16-37 shows a screenshot of the Blackfin loader file viewer utility. The utility is not part of the VisualDSP++ tools LdrViewer suite. It is a third-party freeware product available on http://www.dolomitics.com 16-36 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 659: Determining Boot Stream Start Addresses
Determining Boot Stream Start Addresses The ROM functions ( and others) not only allow the appli- BFROM_SPIBOOT cation to boot a subroutine residing at a given start address, they also assist in walking through linked multi-DXE streams. ADSP-BF59x Blackfin Processor Hardware Reference 16-37...
Page 660: Specific Boot Modes
BFROM_SPIBOOT ADI_BOOT_LOAD_FUNC *pSpiLoadFunction; can be initialized by equipping the hook function with the instruction: pSpiLoadFunction = pBS->pLoadFunction; Specific Boot Modes This section discusses individual boot modes and the required hardware connections. 16-38 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 661: No Boot Mode
When connecting an emulator and starting a debug session, the processor awakens from an idle due to the emulation interrupt and can be debugged in the normal manner. ADSP-BF59x Blackfin Processor Hardware Reference 16-39...
Page 662: Spi Master Boot Modes
0x03 SPI read command or the 0x0B SPI fast read command.  Unlike other Blackfin processors, the ADSP-BF59x Blackfin pro- cessors have no special support for DataFlash devices from Atmel. Nevertheless, DataFlash devices can be used for booting and are sold as standard 24-bit addressable SPI memories.
Page 663 SPI memory con- nected to another GPIO pin. By default, the boot kernel sets the register to a SPI1_BAUD SPI0_BAUD value of 133, resulting in a bit rate of /266 (as shown in Table 16-7). SCLK ADSP-BF59x Blackfin Processor Hardware Reference 16-41...
Page 664: Spi Device Detection Routine
If the received value equals 0xFF, it is assumed that the memory device has not driven its data output yet and that the 0xFF value is due to the pull-up resistor. Thus, another zero byte is transmitted and the received data is 16-42 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 665 SPI memory is connected in SPI master boot mode. After releases, a 0x03 command is transmitted to the output, fol- RESET MOSI lowed by a number of 0x00 bytes. The 24-bit addressable memory device ADSP-BF59x Blackfin Processor Hardware Reference 16-43...
Page 666: Spi Slave Boot Mode
Figure 16-12. Connections Between Host (SPI Master) and Blackfin Pro- cessor (SPI Slave) The host drives the SPI clock and is responsible for the timing. The host must provide an active-low chip select signal that connects to the SPI1_SS 16-44 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 667 HWAIT on-going word. Then, it pauses transmission until releases again. HWAIT SPI1_CLK SPI1_SS SPI1_MOSI SPI1_MISO RESET HWAIT Figure 16-13. Typical SPI Slave Boot Waveforms ADSP-BF59x Blackfin Processor Hardware Reference 16-45...
Page 668 Specific Boot Modes Start Pulse /RESET low Asserted HWAIT Deasserted Assert SPI /SS Asserted HWAIT Deasserted Send Next Byte More Bytes Release SPI /SS EXIT Figure 16-14. SPI Program Flow on Host Device 16-46 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 669: Ppi Boot Mode
The PPI host can synchronize the signal to signal and PPI_FS2 PPI_CLK initiate all data transfers accordingly. The signal can be looped PPI_FS2 back to the . (See Figure 16-15.) PPI_FS1 ADSP-BF59x Blackfin Processor Hardware Reference 16-47...
Page 670 /TMR1 assertions, the master must ensure that the DMA PPI_FS2 completes allowing for the timer to be disabled prior to the com- PWM_OUT pletion of the timer pulse period of 0xFFFFFFFF cycles. PPI_CLK 16-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 671: Uart Slave Mode Boot
Once the byte is received, the host 0x00 can send the entire boot stream. The host should know the total byte count of the boot stream, but it is not required to have any knowledge ADSP-BF59x Blackfin Processor Hardware Reference 16-49...
Page 672 0x40 byte for HWAIT bit rate detection. After the bit rate is known, the UART is enabled and the kernel transmits for bytes. UA0_TX UA0_RX RESET HWAIT Figure 16-18. UART Boot - Host relying on HWAIT 16-50 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 673: Reset And Booting Registers
ROM in the course of developing their own L1 ROM boot sequence.  Analog Devices does not provide technical support for custom boot code development. For more information about custom product and custom IROM mask production, contact your Analog Devices representative.
Page 674: Software Reset (Swrst) Register
Bit 13 indicates the core-double-fault has generated the software reset. Bits [15:13] are read-only and cleared when the register is read. Reading the also clears bits [15:13] in the SWRST SYSCR register. Bits [3:0] are read/write. 16-52 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 675 (Listing 16-1 on page 16-71) and C (Listing 16-2 on page 16-72). It is not recommended that this functional- ity be used directly. Rather, call the ROM function bfrom_SysControl() to perform a system reset. ADSP-BF59x Blackfin Processor Hardware Reference 16-53...
Page 676: System Reset Configuration (Syscr) Register
Ignore WURESET, always perform quick boot. 0100 – BCODE_ALLBOOT Ignore WURESET, do not perform quick boot. 0110 – BCODE_FULLBOOT Ignore WURESET, do not perform quick boot. Update power management 1xxx – reserved Figure 16-20. System Reset Configuration Register 16-54 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 677: Boot Code Revision Control (Bk_Revision)
Enhancements/Bug fix version specifically made for Global boot kernel version number the specific project. Refer to the specific processor anomaly sheet for the version control of a specific silicon revision. Figure 16-21. Boot Code Revision Code (BK_REVISION) ADSP-BF59x Blackfin Processor Hardware Reference 16-55...
Page 678: Boot Code Date Code (Bk_Datecode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xEF00 0050 Bit 31:16 – BK_YEAR Boot Code Date Code BK_DATECODE Word, 15–0 15 14 13 12 11 10 0xEF00 0050 BK_DAY BK_MONTH Figure 16-22. Boot Code Date Code (BK_DATECODE) 16-56 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 679: Zero Word (Bk_Zeros)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xEF00 0048 Read only Zero Word BK_ZEROS, 15–0 15 14 13 12 11 10 0xEF00 0048 Read only Figure 16-23. Zero Word (BK_ZEROS) ADSP-BF59x Blackfin Processor Hardware Reference 16-57...
Page 680: Data Structures
VisualDSP++ users can use these structures directly in assembly programs by using the .IMPORT directive. The structures are supplied by the header file in your bfrom.h VisualDSP++ installation directory. 16-58 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 681: Adi_Boot_Data
The structure is used for any kind of buffer. For the ADI_BOOT_BUFFER user, this structure is important when implementing advanced callback mechanisms. ADI_BOOT_DATA typedef struct { void* pSource; void* pDestination; s16* pControlRegister; s16* pDmaControlRegister; dControlValue; ADSP-BF59x Blackfin Processor Hardware Reference 16-59...
Page 682 ADI_BOOT_DATA load functions, initcode, and callback routines. The structure has two parts. While the first is closely related to internal memory load routines, the second provides access to global boot settings. 16-60 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 683 ADSP-BF59x processors. The HWAIT upper eight bits designate the port number (for example 01 for Port A, 02 for Port B). The lower four bits designate the GPIO in the port. ADSP-BF59x Blackfin Processor Hardware Reference 16-61...
Page 684 If the user sets this value to a negative value, the boot ker- nel exits when the variable increments to zero. variable holds information about the clock divider used by dClock dClock individual (serial) boot modes. 16-62 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 685: Dflags Word
(ADSP-BF59x only) 1 – peripheral boot mode 0 - regular boot 1 - alternate boot BFLAG_NOAUTO 0 – perform automatic device detection 1 – suppress automatic device detection Figure 16-25. dFlags Word (Bits 31–16) ADSP-BF59x Blackfin Processor Hardware Reference 16-63...
Page 686: Callable Rom Functions For Booting
Callable ROM Functions for Booting The following functions support boot management. BFROM_FINALINIT Entry address: 0xEF00 0002 Arguments: no arguments C prototype: void bfrom_FinalInit (void); function never returns. It only executes a bfrom_FinalInit JUMP the address stored in EVT1 16-64 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 687: Bfrom_Mdma
Arguments: pointer to ADI_BOOT_DATA C prototype: void bfrom_MDma (ADI_BOOT_DATA *p); This is the load function used for memory boot modes. This routine is also reused when the or the flags are BFLAG_FILL BFLAG_INDIRECT specified. ADSP-BF59x Blackfin Processor Hardware Reference 16-65...
Page 688: Bfrom_Spiboot
PG11 SPI1_SSEL5 Additional bits in the word are relevant. The user should always set dFlags flag but never the bit. The BFLAG_PERIPHERAL BFLAG_SLAVE flag instructs the system to skip the SPI device detection BFLAG_NOAUTO 16-66 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 689 DMAx_CONFIG pDmaControlRegis- variable in the structure. Similarly, when using a ADI_BOOT_DATA different SPI controller than SPI0, write the MMR address of the relevant register into the variable. SPIx_CTL pControlRegister ADSP-BF59x Blackfin Processor Hardware Reference 16-67...
Page 690: Bfrom_Bootkernel
) point to functional routines. pLoadFunction pErrorFunction BFROM_CRC32 Entry address: 0xEF00 0030 Arguments: • pointer to look-up table in • pointer to data in • dByteCount • initial CRC value in • CRC value returned in 16-68 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 691: Bfrom_Crc32Poly
C prototype: s32 bfrom_Crc32Poly ( unsigned s32 *pLut, s32 dPolynomial); This function generates a 1024-byte look-up table from a given CRC polynomial. During the boot process this routine is hidden by the routine. BFROM_CRC32INITCODE ADSP-BF59x Blackfin Processor Hardware Reference 16-69...
Page 692: Bfrom_Crc32Callback
ADI_BOOT_BUFFER *pCS, s32 dCbFlags); This is a wrapper function that ensures the subroutine fits BFROM_CRC32 into the boot process. BFROM_CRC32INITCODE Entry address: 0xEF00 0036 Arguments: pointer to ADI_BOOT_DATA C prototype: void bfrom_Crc32Initcode ( ADI_BOOT_DATA *p); 16-70 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 693: Programming Examples
To perform a system reset, use the code shown in Listing 16-1 Listing 16-2. Listing 16-1. System Reset in Assembly #include <blackfin.h> P0.L = LO(BFROM_SYSCONTROL); P0.H = HI(BFROM_SYSCONTROL); R0.L = LO(SYSCTRL_SYSRESET); R0.H = HI(SYSCTRL_SYSRESET); R1 = 0; R2 = 0; CALL (P0); ADSP-BF59x Blackfin Processor Hardware Reference 16-71...
Page 694: Exiting Reset To User Mode
The reset handler most likely performs additional tasks not shown in the examples above. Stack pointers and registers are initialized here. EVTx Exiting Reset to Supervisor Mode To exit reset while remaining in supervisor mode, use the code shown in Listing 16-4. 16-72 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 695: Initcode (Power Management Control)
Initcode (Power Management Control) The following examples show how to change PLL and the voltage regula- tor within an initcode. The ADSP-BF59x processors do not have an on-chip voltage regulator. Set the option to bfrom_SysControl SYSCTRL_EXTVOLTAGE ADSP-BF59x Blackfin Processor Hardware Reference 16-73...
Page 696 #define IMM32(reg,val) reg##.H=hi(val); reg##.L=lo(val) .SECTION L1_code; init_DPM: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:5); SP += -12; R0.L = SET_MSEL(12); w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R0; R0.L = (SET_SSEL(4) | CSEL_DIV1); w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllDiv)] = R0; R0.L = 0x0200; 16-74 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 697: Xor Checksum
The routine could BFLAG_INDIRECT xor_callback then perform the checksum calculation at an intermediate storage place. The boot kernel transfers the data from the temporary buffer to the final destination after the callback routine returns. ADSP-BF59x Blackfin Processor Hardware Reference 16-75...
Page 698 ((pCS!= NULL) && (pBS->pHeader!= NULL)) { if (dFlags & CBFLAG_FIRST) { pBS->dUserLong = 0; for (i=0; i<pCS->dByteCount/sizeof(s32); i++) { pBS->dUserLong^= ((s32 *)pCS->pSource)[i]; if (dFlags & CBFLAG_FINAL) { if (pBS->dUserLong!= pBS->pHeader->dArgument) { idle (); return 0; void xor_initcode (ADI_BOOT_DATA *pBS) 16-76 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 699 The checksum algorithm must be booted first and cannot protect itself. The ADSP-BF59x processors provide a CRC32 checksum algorithm in the on-chip L1 instruction ROM, that can be used for booting under this scenario. For more information see “CRC Checksum Calculation” on page 16-30. ADSP-BF59x Blackfin Processor Hardware Reference 16-77...
Page 700 Programming Examples 16-78 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 701: 17 System Design
The CLKIN processor uses the clock input ( ) to generate on-chip clocks. These CLKIN include the core clock ( ) and the peripheral clock ( CCLK SCLK ADSP-BF59x Blackfin Processor Hardware Reference 17-1...
Page 702: Configuring And Servicing Interrupts
Blackfin Processor Programming Reference. Data Delays, Latencies and Throughput For detailed information on latencies and performance estimates on the DMA and external memory buses, refer to “Chip Bus Hierarchy” on page 3-1. 17-2 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 703: Bus Priorities
Although the serial ports may be operated at a slow rate, the output drivers still have fast edge rates and for longer distances the drivers often require resistive termination located at ADSP-BF59x Blackfin Processor Hardware Reference 17-3...
Page 704: Decoupling Capacitors And Ground Planes
Adding termination to fix a problem on an existing board requires delays for new artwork and new boards. A transmission line simulator is recom- mended for critical signals. IBIS models are available from Analog Devices Inc. that will assist signal simulation software. Some signals can be cor- rected with a small zero or 22 ohm resistor located near the driver.
Page 705 Although all capacitors should be kept close to the power consuming device, small capacitance values should be the clos- est and larger values may be placed further from the chip. ADSP-BF59x Blackfin Processor Hardware Reference 17-5...
Page 706: Oscilloscope Probes
(< 0.5 inch) ground clip, attached to the tip of the oscil- loscope probe. The probe should be a low-capacitance active probe with 3 pF or less of loading. The use of a standard ground clip with 17-6 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 707: Recommended Reading
• High-speed properties of logic gates • Measurement techniques • Transmission lines • Ground planes and layer stacking • Terminations • Vias • Power systems • Connectors • Ribbon cables • Clock distribution • Clock oscillators ADSP-BF59x Blackfin Processor Hardware Reference 17-7...
Page 708: Resetting The Processor
If the real-time clock is not used, RTXI should be pulled low. Also note that unused peripherals may have separate power connections. These should be driven to the specified value. 17-8 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 709: Programmable Outputs
This will always indicate 'power good', meaning that V is at a safe operating level. Any delay required at initial DDINT power-on, to guarantee a safe operating level for V , will be pro- DDINT vided by the signal. RESET ADSP-BF59x Blackfin Processor Hardware Reference 17-9...
Page 710 V DDINT signal the processor to start. The voltage at should be calculated such that the V value has risen to the desired voltage range for the DDINT application. 17-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 711: System Mmr Assignments
“PPI Registers” on page A-12 “SPI Controller Registers” on page A-12 “SPORT Controller Registers” on page A-14 “SPORT Clock Gating Register” on page A-17 “UART Controller Registers” on page A-18 “TWI Registers” on page A-19 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 712: Processor-Specific Memory Registers
Processor-specific memory registers (0xFFE0 0004 – 0xFFE0 0300) are listed in Table A-2. Table A-2. Processor-Specific Memory Registers Memory-Mapped Register Name For individual bits, see this diagram: Address 0xFFE0 0300 DTEST_COMMAND “Data Test Command Register” on page 2-5 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 713: Core Timer Registers
Address Name 0xFFC0 0104 SYSCR “System Reset Configuration (SYSCR) Register” on page 16-54 0xFFC0 010C SIC_IMASK0 “System Interrupt Mask (SIC_IMASK) Register” on page 4-12 0xFFC0 0110 SIC_IAR0 “System Interrupt Assignment (SIC_IAR) Register” on page 4-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 714: Dma/Memory Dma Control Registers
Table A-6 identifies the base address of each DMA channel, as well as the register prefix that identifies the channel. Table A-7 then lists the register suffix and provides its offset from the Base Address. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 715 Table A-7. DMA Register Suffix and Offset Register Suffix Offset For individual bits, see this diagram: From Base NEXT_DESC_PTR 0x00 “DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/ MDMA_yy_NEXT_DESC_PTR)” on page 5-80 START_ADDR 0x04 “DMA Start Address Registers (DMAx_START_ADDR/MDMA_yy_START_ADDR)” on page 5-74 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 716 PERIPHERAL_MAP 0x2C “DMA Peripheral Map Registers DMAx_PERIPHERAL_MAP/ MDMA_yy_PERIPHERAL_MAP)” on page 5-66 CURR_X_COUNT 0x30 “DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT /MDMA_yy_CURR_X_COUNT)” on page 5-76 CURR_Y_COUNT 0x38 “DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT)” on page 5-78 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 717: Ports Registers
“GPIO Mask Interrupt B Set Registers” on page 7-29 0xFFC0 072C PORTFIO_MASKB_TOGGLE “GPIO Mask Interrupt B Toggle Registers” on page 7-33 0xFFC0 0730 PORTFIO_DIR “GPIO Direction Registers” on page 7-22 0xFFC0 0734 PORTFIO_POLAR “GPIO Polarity Registers” on page 7-25 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 718 “GPIO Mask Interrupt B Toggle Registers” on page 7-33 0xFFC0 1530 PORTGIO_DIR “GPIO Direction Registers” on page 7-22 0xFFC0 1534 PORTGIO_POLAR “GPIO Polarity Registers” on page 7-25 0xFFC0 1538 PORTGIO_EDGE “Interrupt Sensitivity Registers” on page 7-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 719: Timer Registers
“Timer Period (TIMER_PERIOD) and Timer Width (TIMER_WIDTH) Registers” on page 8-42 0xFFC0 060C TIMER0_WIDTH “Timer Period (TIMER_PERIOD) and Timer Width (TIMER_WIDTH) Registers” on page 8-42 0xFFC0 0610 TIMER1_CONFIG “Timer Configuration Register (TIMER_CONFIG)” on page 8-40 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 720 Width (TIMER_WIDTH) Registers” on page 8-42 0xFFC0 0680 TIMER_ENABLE “Timer Enable Register (TIMER_ENABLE)” on page 8-35 0xFFC0 0684 TIMER_DISABLE “Timer Disable Register (TIMER_DISABLE)” on page 8-36 0xFFC0 0688 TIMER_STATUS “Timer Status Register (TIMER_STATUS)” on page 8-38 A-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 721: Watchdog Timer Registers
“PLL_CTL Register” on page 6-20 0xFFC0 0004 PLL_DIV “PLL_DIV Register” on page 6-19 0xFFC0 0008 VR_CTL “VR_CTL Register” on page 6-21 0xFFC0 000C PLL_STAT “PLL_STAT Register” on page 6-20 0xFFC0 0010 PLL_LOCKCNT “PLL_LOCKCNT Register” on page 6-21 ADSP-BF59x Blackfin Processor Hardware Reference A-11...
Page 722: Ppi Registers
For individual bits, see this diagram: Address 0xFFC0 0500 SPI0_CTL “SPI Control (SPI_CTL) Register” on page 13-35 0xFFC0 0504 SPI0_FLG “SPI Flag (SPI_FLG) Register” on page 13-37 0xFFC0 0508 SPI0_STAT “SPI Status (SPI_STAT) Register” on page 13-38 A-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 723 0xFFC0 3410 SPI1_RDBR “SPI Receive Data Buffer (SPI_RDBR) Register” on page 13-42 0xFFC0 3414 SPI1_BAUD “SPI Baud Rate (SPI_BAUD) Register” on page 13-34 0xFFC0 3418 SPI1_SHADOW “SPI RDBR Shadow (SPI_SHADOW) Register” on page 13-43 ADSP-BF59x Blackfin Processor Hardware Reference A-13...
Page 724: Sport Controller Registers
(SPORT_TCLKDIV and SPORT_RCLKDIV) Registers” on page 14-61 0xFFC0 082C SPORT0_RFSDIV “SPORT Transmit and Receive Frame Sync Divider (SPORT_TFSDIV and SPORT_RFSDIV) Registers” on page 14-62 0xFFC0 0830 SPORT0_STAT “SPORT Status (SPORT_STAT) Register” on page 14-60 A-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 725 Register Name For individual bits, see this diagram: Address 0xFFC0 0900 SPORT1_TCR1 “SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers” on page 14-46 0xFFC0 0904 SPORT1_TCR2 “SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers” on page 14-46 ADSP-BF59x Blackfin Processor Hardware Reference A-15...
Page 726 “SPORT Multichannel Configuration (SPORT_MCMC1 and SPORT_MCMC2) Registers” on page 14-63 0xFFC0 0940 SPORT1_MTCS0 “SPORT Multichannel Transmit Selection (SPORT_MTCSn) Registers” on page 14-66 0xFFC0 0944 SPORT1_MTCS1 “SPORT Multichannel Transmit Selection (SPORT_MTCSn) Registers” on page 14-66 A-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 727: Sport Clock Gating Register
The SPORT clock gating register (0xFFC0 120C) is listed in Table A-18. Table A-17. SPORT Clock Gating Register Memory-Mapped Register Name For individual bits, see this diagram: Address 0xFFC0 120C SPORT_CLKGATE “SPORT Clock Gating Register” on page 14-76 ADSP-BF59x Blackfin Processor Hardware Reference A-17...
Page 728: Uart Controller Registers
11-23 0xFFC0 0414 UART_LSR “UART Line Status (UART_LSR) Register” on page 11-24 0xFFC0 041C UART_SCR “UART Scratch (UART_SCR) Register” on page 11-30 0xFFC0 0424 UART_GCTL “UART Global Control (UART_GCTL) Register” on page 11-31 A-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 729: Twi Registers
TWI_FIFO_CTL “TWI FIFO Control Register (TWI_FIFO_CTL)” on page 12-36 0xFFC0 142C TWI_FIFO_STAT “TWI FIFO Status Register (TWI_FIFO_STAT)” on page 12-38 0xFFC0 1480 TWI_XMT_DATA8 “TWI FIFO Transmit Data Single Byte Register (TWI_XMT_DATA8)” on page 12-43 ADSP-BF59x Blackfin Processor Hardware Reference A-19...
Page 730 “TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16)” on page 12-43 0xFFC0 1488 TWI_RCV_DATA8 “TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8)” on page 12-44 0xFFC0 148C TWI_RCV_DATA16 “TWI FIFO Receive Data Double Byte Register (TWI_RCV_DATA16)” on page 12-45 A-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 731: Test Features
• Testing the integrated circuit itself • Observing or modifying circuit activity during normal component operation The test logic consists of a boundary-scan register and other building blocks. The test logic is accessed through a Test Access Port (TAP). ADSP-BF59x Blackfin Processor Hardware Reference...
Page 732: Boundary-Scan Architecture
1 or logic 0 state. For full details of the operation, see the JTAG standard. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 733 Test Features Figure B-1 shows the state diagram for the TAP controller. Test-Logic_Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR Capture-IR Shift-IR Shift-DR Exit1-IR Exit1-DR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR Figure B-1. TAP Controller State Diagram ADSP-BF59x Blackfin Processor Hardware Reference...
Page 734: Instruction Register
The register column lists the serial scan paths. Table B-2. Decode for Public JTAG-Scan Instructions Instruction Name Binary Decode Register 01234 EXTEST 00000 Boundary-Scan SAMPLE/PRELOAD 10000 Boundary-Scan BYPASS 11111 Bypass ADSP-BF59x Blackfin Processor Hardware Reference...
Page 735: Public Instructions
Table B-2. Boundary-Scan Register Bypass Register JTAG Instruction Register Figure B-2. Serial Scan Paths Public Instructions The following sections describe the public JTAG scan instructions. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 736: Extest - Binary Code 00000
BYPASS – Binary Code 11111 instruction selects the register to be connected to BYPASS BYPASS . The instruction has no effect on the internal logic. No data inversion should occur between ADSP-BF59x Blackfin Processor Hardware Reference...
Page 737: Boundary-Scan Register
Test Features Boundary-Scan Register The boundary-scan register is selected by the EXTEST SAMPLE/PRELOAD instructions. These instructions allow the pins of the processor to be con- trolled and sampled for board-level testing. ADSP-BF59x Blackfin Processor Hardware Reference...
Page 738 Boundary-Scan Architecture ADSP-BF59x Blackfin Processor Hardware Reference...
Page 739: Index
BFLAG_CALLBACK bit, 16-12, 16-64 12-33, 12-35 BFLAG_FASTREAD bit, 16-63 application data, loading, 16-1 BFLAG_FILL bit, 16-12, 16-64 arbitration BFLAG_FINAL bit, 16-12, 16-64 DAB, BFLAG_FIRST bit, 16-64 DCB, BFLAG_first bit, 16-12 TWI, 12-8 BFLAG_HDRINDIRECT bit, 16-63 architecture, memory, ADSP-BF59x Blackfin Processor Hardware Reference...
Page 740 BKZEROS (boot code zeros) register, boot code revision (BKREVISION) 16-57 register, 16-55 Blackfin processor family boot code zero word (BK_ZEROS) memory architecture, register, 16-57 block, DMA, boot host wait block code field, 16-12 HWAIT, 16-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 741 8-46 bandwidth, clock core, clock signals, 1-16 hierarchy, control, on-chip, external, 1-16 PAB, frequency for SPORT, 14-61 peripheral, internal, and peripherals, managing, 17-1 prioritization and DMA, 5-48 peripheral, bus standard, I source for general-purpose timers, ADSP-BF59x Blackfin Processor Hardware Reference...
Page 742 (CCLK), 6-5, 17-2 current address registers core clock/system clock ratio control, (DMAx_CURR_ADDR), 5-74 timer, (MDMA_yy_CURR_ADDR), 5-74 waking from idle state, current descriptor pointer core and system reset, code example, 16-71, (DMAx_CURR_DESC_PTR) 16-72 registers, 5-81 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 743 PPI, 15-16 15-18 DFRESET bit, 16-54 data structures, 16-58 DI_EN bit, 5-14, 5-67, 5-69 boot_struct, 16-60 direct code execution buffer_struct, 16-59 initial header, 16-20 header_struct, 16-59 direct memory access, See DMA ADSP-BF59x Blackfin Processor Hardware Reference...
Page 744 5-100 continuous transition, 5-26 initializing, 5-17 control command restrictions, 5-34 internal interfaces, control commands, 5-31, 5-32 and L1 memory, controllers, large model mode, 5-69 data transfers, latency, 5-24 descriptor array, 5-22 memory conflict, 5-48 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 745 5-52 work units, 5-14, 5-22, 5-24 small model mode, 5-68 DMA2D bit, 5-67, 5-70 software management, 5-50 DMA bus, See DAB software-triggered descriptor fetch DMACFG field, 5-21, 5-61 example, 5-96 DMA channel registers, 5-62 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 746 DMAx_CURR_ADDR (current address) DTEST_COMMAND (data test registers, 5-74 command) register, DMAx_CURR_DESC_PTR (current DTxPRI signal, 14-5 descriptor pointer) registers, 5-81 DTxPRI SPORT output, 14-5 DMAx_CURR_X_COUNT (current DTxSEC signal, 14-5 inner loop count) registers, 5-76 DTxSEC SPORT output, 14-5 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 747 ERR_TYP[1:0] field, 8-7, 8-40, 8-41, 8-46 general-purpose timers interrupt ERR_TYP bits, 8-28 structure, ETBEI (enable transmit buffer empty GPIO, 7-17 interrupt) bit, 11-6, 11-11, 11-17, GPIO interrupt generation, 7-14 11-26, 11-27 PPI, 15-24 event controller, SPI core-driven, 13-29 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 748 8-43 frame track error, 15-30, 15-33 capture mode, frequencies, clock and frame sync, 14-25 clock source, FSDR (frame sync to data relationship) bit, code examples, 8-47 14-21, 14-64 control bit summary, 8-45 I-10 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 749 8-17 set registers, 7-10 two timers with non-overlapping clocks, toggle registers, 7-11 8-17 using as input, waveform generation, 8-13 write operations, WDTH_CAP mode, 8-23, 8-43 writes to registers, 7-10 WDTH_CAP mode configuration, 8-55 ADSP-BF59x Blackfin Processor Hardware Reference I-11...
Page 750 7-24 handshaking memory DMA (HMDMA), GPIO toggle (PORTxIO_TOGGLE) registers, 7-25 hardware reset, 16-3, 16-4, 16-6 GP modes, PPI, 15-14 HDRCHK field, 16-12 ground plane, 17-4, 17-5 HDRSGN field, 16-12 header checksum field HDRCHK, 16-15 I-12 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 751 14-10 (ITEST_COMMAND), serial devices, 14-3 interfaces ICPLB_DATAx (instruction CPLB data) on-chip, register, overview, idle state system, waking from, inter IC bus, 12-2 IEEE 1149.1 standard, See JTAG standard interlaced video, 15-6 ADSP-BF59x Blackfin Processor Hardware Reference I-13...
Page 752 GPIO interrupts, 7-15 I/O pins, general-purpose, general-purpose, 4-2, IRCLK (internal receive clock select) bit, general-purpose timers, 8-4, 8-5, 8-14, 14-52, 14-54 8-28 IrDA, 11-31 generated by peripherals, receiver, 11-9 GPIO, 7-11, 7-13, 7-16 transmitter, 11-8 I-14 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 753 LOOP (loopback mode enable) bit, 11-23 LOSTARB (lost arbitration) bit, 12-33, 12-35 JTAG, 1-21, B-1, B-2, LRFS (low receive frame sync select) bit, 14-12, 14-31, 14-32, 14-52, 14-55 LSBF (LSB first) bit, 13-36 LT_ERR_OVR flag, 15-31 data memory, ADSP-BF59x Blackfin Processor Hardware Reference I-15...
Page 754 5-46, 5-47, 5-88 14-37 MDMA_yy_CONFIG (DMA on-chip, configuration) registers, 5-67 start locations of L1 instruction memory MDMA_yy_CURR_ADDR (current subbanks, address) registers, 5-74 structure, MDMA_yy_CURR_DESC_PTR (current memory conflict, DMA, 5-48 descriptor pointer) registers, 5-81 I-16 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 755 NINT (pending interrupt) bit, 11-28, multichannel, 14-14 11-29 serial port, 14-10 normal frame sync mode, 14-34 SPI master, 13-14, 13-17 normal timing, serial port, 14-34 SPI slave, 13-15, 13-19 NTSC systems, 15-6 UART DMA, 11-17 UART non-DMA, 11-15 ADSP-BF59x Blackfin Processor Hardware Reference I-17...
Page 756 Peripheral bus (DMAx_Y_COUNT), 5-78 errors generated by SPORT, 14-38 (MDMA_yy_Y_COUNT), 5-78 peripheral DMA start address registers, output pad disable, timer, 8-12 5-74 overflow interrupt, DMA, 5-40 peripheral interrupts, 4-2, 4-3, I-18 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 757 PLL, 6-28 sleep mode, active (enabled but bypassed) mode, STOPCK bit, 6-10 active mode, voltage control, applying power to the PLL, 6-11 PLL control (PLL_CTL) register, 6-3, 6-4, block diagram, 6-19, 6-20 BYPASS bit, ADSP-BF59x Blackfin Processor Hardware Reference I-19...
Page 758 7-16 PORTxIO_MASKA_SET (GPIO mask peripherals, 7-2, interrupt A set) registers, 7-28 structure, PORTxIO_MASKA_SET registers, 7-28 PORTG_FER (function enable) register, PORTxIO_MASKA_TOGGLE (GPIO mask interrupt A toggle) registers, PORTG_HYSTERESIS register, 7-19, 7-32 7-20 PORTxIO_MASKA_TOGGLE registers, 7-32 I-20 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 759 GP output, 15-19 power-on reset, 16-3 hardware signalling, 15-16 PPI, 15-2 15-37 horizontal tracking, 15-31 active video only mode, 15-10 interlaced video, 15-6 block diagram, 15-3 internal frame sync modes, 15-16 internal frame syncs, 15-16 ADSP-BF59x Blackfin Processor Hardware Reference I-21...
Page 760 PULSE_HI bit, 8-14, 8-16, 8-24, 8-41, PPI_CLK signal, 15-25 8-45 PPI_CONTROL (PPI control) register, PULSE_HI toggle mode, 8-15 15-25, 15-26 pulse width count and capture mode, See PPI control register (PPI_CONTROL), WDTH_CAP mode 15-25, 15-26 I-22 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 761 RESET_WDOG bit, 10-5, 16-52 length) bit, 12-36 restart control command, DMA, 5-32, RCVSERVM (receive FIFO service 5-33 interrupt mask) bit, 12-40 restart or finish control command, RCVSERV (receive FIFO service) bit, transmit, 5-34, 5-35 12-40, 12-41 ADSP-BF59x Blackfin Processor Hardware Reference I-23...
Page 762 SDIR (slave transfer direction) bit, 12-28, RXS (RX data buffer status) bit, 13-22, 12-29 13-39 SEN (slave enable) bit, 12-26, 12-27 serial clock frequency, 13-34 communications, 11-5 SADDR[6:0] field, 12-28 data transfer, 14-4 SAMPLE/PRELOAD instruction, I-24 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 763 SPI system, 13-35 slaves error interrupt, 13-16 PAB, error signals, 13-38 13-41 slave select, SPI, 13-37 features, 13-2 slave SPI device, 13-5 full-duplex synchronous serial interface, sleep mode, 1-17, 13-2 general operation, 13-14 13-21 ADSP-BF59x Blackfin Processor Hardware Reference I-25...
Page 764 DMA data packing, 14-23 word length, 13-35 enable/disable, 14-9 SPI_BAUD (SPI baud rate) register, 13-33, enabling multichannel mode, 14-17 13-34 framed serial transfers, 14-31 SPI_BAUD values, 13-34 framed vs. unframed, 14-30 frame sync, 14-31, 14-34 I-26 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 765 14-17 frame sync divider) registers, 14-62 stereo serial operation, 14-10 SPORTx_RX (SPORTx receive data) support for standard protocols, 14-24 registers, 14-18, 14-58 termination, 14-8 SPORTx_STAT (SPORTx status) throughput, 14-5 registers, 14-60 ADSP-BF59x Blackfin Processor Hardware Reference I-27...
Page 766 16-6 peripheral interrupt events, 4-17 support, technical or customer, xxxiv registers, 4-10 surface-mount capacitors, 17-5 system interrupt mask (SIC_IMASK) SWRESET bit, 16-54 register, SWRST, software reset register, 16-52 system peripheral clock, See SCLK I-28 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 767 (TIMILx) bits, 8-4, 8-39 test features, timer period[15:0] field, 8-44 testing circuit boards, B-1, timer period[31:16] field, 8-44 test-logic-reset state, timer period (TIMERx_PERIOD) test point access, 17-6 registers, 8-4, 8-43, 8-44 TFS pins, 14-30, 14-36 ADSP-BF59x Blackfin Processor Hardware Reference I-29...
Page 768 TMODE[1:0] field, 8-11, 8-41, 8-45 SPORTx_TCR2), 14-46 TMPWR bit, 9-3, transmit data[15:0] field, 14-57 TMRCLK input, 8-58 transmit data[31:16] field, 14-57 TMREN bit, 9-3, transmit data buffer[15:0] field, 13-42 TMR pin, 8-46 transmit hold[7:0] field, 11-26 I-30 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 769 TWI_CONTROL (TWI control) register, baud rate, 11-7 12-4, 12-25 baud rate examples, 11-13 TWI_ENA bit, 12-25 bit rate examples, 11-13 TWI_FIFO_CTL (TWI FIFO control) bit rate generation, 11-12 register, 12-36 bitstream, 11-6 block diagram, 11-3 ADSP-BF59x Blackfin Processor Hardware Reference I-31...
Page 770 11-6, 11-19, 11-26 registers, table, 11-19 UCEN (enable UART clocks) bit, 11-7, sampling clock period, 11-8 11-12, 11-30, 11-31 standard, 11-2 UNDR (FIFO underrun) bit, 15-30, 15-31 string transmission, 11-36 unframed/framed, serial data, 14-30 I-32 ADSP-BF59x Blackfin Processor Hardware Reference...
Page 771 WDTH_CAP mode, 8-23, 8-43 register, 6-19, 6-21 control bit and register usage, 8-45 WLS[1:0] field, 11-21 WNR bit, 5-70 WNR (DMA direction) bit, 5-67, 5-70 W1C operations, 5-10 WOFF[9:0] field, 14-21, 14-64 wakeup function, ADSP-BF59x Blackfin Processor Hardware Reference I-33...
Page 772 (W1C) operations, 5-10 write operation, GPIO, YCbCr format, 15-27 WSIZE[3:0] field, 14-20, 14-64 Y_COUNT[15:0] field, 5-78 WURESET bit, 16-54 Y_MODIFY[15:0] field, 5-79 X_COUNT[15:0] field, 5-75 µ-law companding, 14-23, 14-28 XFR_TYPE[1:0] field, 15-4, 15-26, 15-29 I-34 ADSP-BF59x Blackfin Processor Hardware Reference...