Analog Devices ADSP-BF506F Hardware Reference Manual page 829

3. The processor core writes to the
more of the SPI flag select bits (
4. The processor core writes to the
enabling the device as a master and configuring the SPI system by
specifying the appropriate word length, transfer format, baud rate,
and so on. The
"receive with DMA" (
( =
TIMOD
5. If configured for receive, a receive transfer is initiated upon
enabling of the SPI. Subsequent transfers are initiated as the SPI
reads data from the
FIFO. The SPI then requests a DMA write to memory. Upon a
DMA grant, the DMA engine reads a word from the SPI DMA
FIFO and writes to memory.
If configured for transmit, the SPI requests a DMA read from
memory. Upon a DMA grant, the DMA engine reads a word from
memory and writes to the SPI DMA FIFO. As the SPI writes data
from the SPI DMA FIFO into the
transfer on the SPI link.
6. The SPI then generates the programmed clock pulses on
simultaneously shifts data out of
For receive transfers, the value in the shift register is loaded into
the
SPI_RDBR
fers, the value in the
register at the start of the transfer.
7. In receive mode, as long as there is data in the SPI DMA FIFO (the
FIFO is not empty), the SPI continues to request a DMA write to
memory. The DMA engine continues to read a word from the SPI
DMA FIFO and writes to memory until the SPI DMA word count
register transitions from "1" to "0". The SPI continues receiving
words until SPI DMA mode is disabled.
ADSP-BF50x Blackfin Processor Hardware Reference
field should be configured to select either
TIMOD
TIMOD
) mode.
b#11
SPI_RDBR
register at the end of the transfer. For transmit trans-
SPI_TDBR
SPI-Compatible Port Controller
register, setting one or
SPI_FLG
).
FLSx
and
SPI_BAUD
= ) or "transmit with DMA"
b#10
register and writes to the SPI DMA
register, it initiates a
SPI_TDBR
and shifts data in from
MOSI
register is loaded into the shift
registers,
SPI_CTL
and
SCK
MISO
18-25
.