Analog Devices ADSP-BF506F Hardware Reference Manual page 308

DMA Registers
DMA Interrupt Status Registers
(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS)
The DMAx_IRQ_STATUS register, shown in
that record whether the DMA channel:
• Is enabled and operating, enabled but stopped, or disabled.
• Is fetching data or a DMA descriptor.
• Has detected that a global DMA interrupt or a channel interrupt is
being asserted.
• Has logged occurrence of a DMA error.
Note the
DMA_DONE
or write) has completed.

For a memory transfer to a peripheral, there may be up to four data
words in the channel's DMA FIFO when the interrupt occurs. At
this point, it is normal to immediately start the next work unit. If,
however, the application needs to know when the final data item is
actually transferred to the peripheral, the application can test or
poll the
in the FIFO, the

For a memory write DMA channel, the state of the
no meaning after the last
not indicate the status of the DMA FIFO.
For MDMA transfers where an interrupt is not desired to notify
when the DMA operation has ended, software should poll the
DMA_DONE
transaction has completed.
7-72
interrupt is asserted when the last memory access (read
bit. As long as there is undelivered transmit data
DMA_RUN
bit is 1.
DMA_RUN
DMA_DONE
bit, rather than the
ADSP-BF50x Blackfin Processor Hardware Reference
Figure 7-7, contains bits
event has been signaled. It does
bit to determine when the
DMA_RUN
bit has
DMA_RUN