Command Interface To Internal Flash Memory - Analog Devices ADSP-BF506F Hardware Reference Manual

Command Interface to Internal Flash Memory

The device includes a protection register to increase the protection of a
system's design. The protection register is divided into two segments: a
64-bit segment containing a unique device number and a 128-bit segment
one-time-programmable (OTP) by the user. The user programmable
segment can be permanently protected.
protection register memory map.
Command Interface to Internal Flash
Memory
All bus write operations to the internal flash memory device are inter-
preted by the command interface. Commands consist of one or more
sequential bus write operations. An internal program/erase controller
manages all timings and verifies the correct execution of the program and
erase commands. The program/erase controller provides a status register
whose output may be read at any time to monitor the progress or the
result of the operation.
The command interface is reset to read mode when power is first applied
or when exiting from reset. Command sequences must be followed
exactly. Any invalid combination of commands is ignored.
Refer to Table 6-4
for a summary of the command interface.
Table 6-4. Command Codes
Hex Code
0x01
0x03
0x10
0x20
0x2F
6-6
and "Command Interface State Tables" on page 6-68
Command
Block Lock Confirm
Set Configuration Register Confirm
Alternative Program Setup
Block Erase Setup
Block Lock-Down Confirm
ADSP-BF50x Blackfin Processor Hardware Reference
Figure 6-2 on page 6-18 shows the