Software-Triggered Descriptor Fetches - Analog Devices ADSP-BF506F Hardware Reference Manual

active queue. The interrupt handler should then pass a message back to
the non-interrupt software indicating the location of the last descriptor
accepted into the active queue. If, on the other hand, the interrupt han-
dler reads its mailbox and finds a
there is no more work to perform, then it should pass an appropriate mes-
sage (for example zero) back to the non-interrupt software indicating that
the queue has stopped. This simple handler should be able to be coded in
a very small number of instructions.
The non-interrupt software which accepts new DMA work requests needs
to synchronize the activation of new work with the interrupt handler. If
the queue has stopped (the mailbox from the interrupt software is zero),
the non-interrupt software is responsible for starting the queue (writing
the first descriptor's
ister). If the queue is not stopped, the non-interrupt software must not
write to the
DMAx_CONFIG
Instead the descriptor should queue to the waiting queue, and update its
mailbox directed to the interrupt handler.

Software-Triggered Descriptor Fetches

If a DMA has been stopped in
DMAx_IRQ_STATUS
DMA FIFOs has been completely processed. Once the
it is safe to restart the DMA by simply writing again to the
register. The DMA sequence is repeated with the previous settings.
Similarly, a descriptor-based DMA sequence that has been stopped tem-
porarily with a
the configuration register. When the DMA controller detects the
condition by loading the
updated the next descriptor pointer, regardless of whether operating in
descriptor array mode or descriptor list mode.
The next descriptor pointer remains valid if the DMA halts and is
restarted. As soon as the
ADSP-BF50x Blackfin Processor Hardware Reference
DMAx_CONFIG
register (which would cause a DMA error).
FLOW
register remains set until the content of the internal
= 0 descriptor can be continued with a new write to
FLOW
field from memory, it has already
DMACFG
DMA_RUN
Direct Memory Access
value of zero, indicating
DMAx_CONFIG
value to the channel's
= 0 mode, the
DMA_RUN
bit clears, software can restart the DMA
reg-
DMAx_CONFIG
bit in the
bit clears,
DMA_RUN
DMAx_CONFIG
= 0
FLOW
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