Table of Contents
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CAN Register Definitions
Mailbox Control Registers
Figure 17-30
through
CAN_MCx Registers
Mailbox Configuration Register 1 (CAN_MC1)
For all bits, 0 - Mailbox disabled, 1 - Mailbox enabled
15 14 13 12 11 10
0
0xFFC0 2A00
MC15
MC14
MC13
MC12
MC11
MC10
MC9
MC8
Figure 17-30. Mailbox Configuration Register 1
Mailbox Configuration Register 2 (CAN_MC2)
For all bits, 0 - Mailbox disabled, 1 - Mailbox enabled
15 14 13 12 11 10
0
0xFFC0 2A40
MC31
MC30
MC29
MC28
MC27
MC26
MC25
MC24
Figure 17-31. Mailbox Configuration Register 2
17-68
Figure 17-56
9
8
7
0
0
0
0
0
0
0
0
9
8
7
0
0
0
0
0
0
0
0
ADSP-BF50x Blackfin Processor Hardware Reference
show the mailbox control registers.
6
5
4
3
2
1
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Reset = 0x0000
MC0
MC1
MC2
MC3
MC4
MC5
MC6
MC7
Reset = 0x0000
MC16
MC17
MC18
MC19
MC20
MC21
MC22
MC23
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