Uart Transmit Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

IrDA support is enabled by setting the
The IrDA application requires external transceivers.

UART Transmit Operation

Receive and transmit paths operate completely independently except that
the bit rate and the frame format are identical for both transfer directions.
Transmission is initiated by writes to the UARTx_THR register. If no for-
mer operation is pending, the data is immediately passed from the
UARTx_THR register to the internal TSR register where it is shifted out
at a bit rate characterized by the formula that follows with start, stop, and
parity bits appended as defined by the UARTx_LCR register:
The least significant bit (LSB) is always transmitted first. This is bit 0 of
the value written to
Writes to the
UARTx_THR
to the transmit shift registers (
UARTx_THR
again.
LSR
When enabled by the
requests an interrupt on the dedicated
through the DMA controller. If the associated DMA channel is enabled,
the signal functions as a DMA request, otherwise the DMA control-
TXREQ
ler simply forwards it to the SIC interrupt controller. If no DMA channel
is assigned to the UART, the
rect the receive and transmit interrupts to the UART status interrupt
alternatively.
The
UARTx_THR
two-stage transmit buffer. When data is pending in either one of these reg-
isters, the
TEMT
ADSP-BF50x Blackfin Processor Hardware Reference
= ---------------------------------------------------- -
BIT RATE
16
.
UARTx_THR
register clear the
bit in the
ETBEI
EGLSI
register and the internal
flag is low. As soon as all data has left the
UART Port Controllers
bit in the
IREN
SCLK
 
– 
1 EDB0
Divisor
flag. Transfers of data from
THRE
) set this status flag in
TSR
register, the
UARTx_IER
output. This signal is routed
TXREQ
bit in the
UARTx_GCTL
register can be seen as a
TSR
register.
UARTx_GCTL
UARTx_
flag
THRE
register can redi-
register, the
TSR
15-7