Rsi Status Clear Register (Rsi_Statuscl) - Analog Devices ADSP-BF506F Hardware Reference Manual

RSI Registers
Table 21-20. RSI_STATUS Register (Cont'd)
Bit Name
19 RX_DAT_ZERO
20 TX_DAT_RDY
21 RX_FIFO_RDY
31:22 Reserved

RSI Status Clear Register (RSI_STATUSCL)

The
RSI_STATUSCL
register. Write a "1" to any of the bits to clear the
RSI_STATUS
corresponding flag in the
RSI Status Clear Register (RSI_STATUSCL)
Write 1 Action
15 14 13 12 11 10
0xFFC0 3838
0
Reserved
DAT_BLK_END_STAT
START_BIT_ERR_STAT
DAT_END_STAT
Figure 21-17. RSI Status Clear Register
21-68
Function
Receive FIFO empty
0 = Not empty
1 = Receive FIFO empty
Transmit data available
0 = No data
1 = Data available in transmit
FIFO
Receive data available
0 = No data
1 = Data available in receive FIFO
Reserved
register is used to clear the static flags of the
RSI_STATUS
9 8 7
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
register.
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Type Default
RO 0
RO 0
RO 0
RO 0
Reset = 0x0000
CMD_CRC_FAIL_STAT
DAT_CRC_FAIL_STAT
CMD_TIMEOUT_STAT
DAT_TIMEOUT_STAT
TX_UNDERRUN_STAT
RX_OVERRUN_STAT
CMD_RESP_END_STAT
CMD_SEND_STAT