Pwm Duty Cycle Pwm_Cha, Pwm_Chb, And Pwm_Chc) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
information is provided by the
which is cleared during operation in the first half of each PWM period
(between the rising edge of the original
of the second
PWM_SYNC
bit is set during operation in the second half of each PWM
PWM_PHASE
period. This status bit allows determination of the particular half-cycle
during implementation of the
The advantage of double-update mode is that the PWM process can pro-
duce lower harmonic voltages, and faster control bandwidths are possible.
However, for a given PWM switching frequency,
twice the rate in double-update mode. Since new duty cycle values are
computed in each
mode places a larger computational burden on the processor.
Alternatively, the same PWM update rate may be maintained at half the
switching frequency, yielding lower switching losses.
The
PWM_STAT2
register contains the output values of all the three pairs of PWM signals
( ,
PWM_AH PWM_AL
PWM Duty Cycle (PWM_CHA, PWM_CHB, and
PWM_CHC) Registers
Three 16-bit read/write duty cycle registers (
) control the duty cycles of the six PWM output signals on the
PWM_CHC
,
PWM_AH PWM_AL
switched reluctance mode. The two's complement integer value in the
register controls the duty cycle of the signals on the
PWM_CHA
outputs; in
PWM_AL
and
PWM_BH PWM_BL
and
PWM_CH PWM_CL
complement integer counts of the fundamental time unit (t
define the desired on-time of the high-side PWM signal produced by the
Three-Phase PWM Timing Unit over half the PWM period.
14-14
PWM_PHASE
pulse introduced in double-update mode). The
PWM_SYNC
interrupt service routine, double-update
PWM_SYNCINT
status register is provided for software simulation. This
, , ,
PWM_BH PWM_BL
, , ,
PWM_BH PWM_BL PWM_CH
, it controls the duty cycle of the signals on
PWM_CHB
; in , it controls the duty cycle of the signals on
PWM_CHC
. The duty cycle registers are programmed in two's
ADSP-BF50x Blackfin Processor Hardware Reference
bit of the
pulse and the rising edge
PWM_SYNC
interrupt service routine.
PWM_SYNC
, and
PWM_CH PWM_CL
PWM_CHA
, and
PWM_CL
register,
PWM_STAT
pulses occur at
).
, , and
PWM_CHB
pins when not in
and
PWM_AH
) and
SCLK