Analog Devices ADSP-BF506F Hardware Reference Manual page 636

UART Registers
The bit enables interrupt generation on an independent interrupt
ELSI
channel when any of the following conditions are raised by the respective
bit in the
UARTx_LSR
• Receive overrun error (
• Receive parity error (
• Receive framing error (
• Break interrupt (
The bit enables a modem status interrupt on the same status inter-
EDSSI
rupt channel when the
indicates CTS re-assertion. Write-1-to-clear (W1C) the
the interrupt request.
The bit enables the receive buffer threshold interrupt if signalled by
ERFCI
the bit. Read the
RFCS
interrupt request.
The bit enables interrupt generation on the status interrupt channel
ETFI
when both the transmit buffer register and transmit shift register are
empty as indicated by the
interrupt can be used to avoid expensive polling of the
UART clock or line drivers should be disabled after transmission has com-
pleted. W1C the
the bit's functionality might be preferred.
ETDPTI
The bit is required for DMA transmit operation only. It enables
ETDPTI
the DMA completion interrupt to be delayed until the data has left the
UART completely. If set, it can generate a DMA interrupt by the time the
bit goes high after the last DMA data word is transmitted.
TEMT
If the bit is cleared, the DMA completion interrupt is generated
ETDPTI
when either the last data word is transferred from memory to the DMA
FIFO (DMA's
FIFO ( bit set). If
SYNC
15-42
register:
)
OE
)
PE
)
FE
)
BI
bit in the
SCTS
UARTx_RBR
bit in the
TFI
bit to clear the interrupt request. In DMA operation,
TFI
bit cleared) or when the last word has left the DMA
SYNC
is set, usually the DMA's
ETDPTI
ADSP-BF50x Blackfin Processor Hardware Reference
register is set. This
UARTx_MSR
register sufficient times to clear the
register. The
UARTx_LSR
bit to clear
SCTS
ETFI
bit, when the
TEMT
is not set in
DI_EN