Switched Reluctance Mode; Output Control Unit - Analog Devices ADSP-BF506F Hardware Reference Manual

Switched Reluctance Mode

A general-purpose mode utilizing independent edge placement of upper
and lower signals of each of the three PWM channels is incorporated into
the Three-Phase PWM Timing Unit. This mode is provided for SR motor
operation and is described in detail in
on page 14-31.

Output Control Unit

The operation of the Output Control Unit is controlled by the 9-bit
read/write
PWM_SEG
features that are useful in the control of ECMs or BDCMs.
Crossover Feature
The register contains three crossover bits—one for each pair of
PWM_SEG
PWM outputs. Setting the
crossover mode for the
enables crossover on the
over on the /
CH
signals, the high-side PWM signal (for example,
PWM Timing Unit is diverted to the associated low-side output of the
Output Control Unit so that the signal ultimately appears at the
The corresponding low-side output of the Three-Phase PWM Timing
Unit is also diverted to the complementary high-side output of the Out-
put Control Unit so that the signal appears at the
reset, the three crossover bits are cleared, disabling crossover mode on all
three pairs of PWM signals. Even though crossover is considered an out-
put control feature, dead time insertion occurs after crossover transitions
(as necessary to eliminate shoot-through safety issues).
ADSP-BF50x Blackfin Processor Hardware Reference
register (on page
AHAL_XOVR
/ pair of PWM signals, setting
AH AL
/ pair, and setting
BH BL
pair. If crossover mode is enabled for any pair of PWM
CL
"Switched Reluctance (SR) Mode"
14-45) that controls two distinct
bit of the
PWM_SEG
CHCL_XOVR
) from the Three-Phase
AH
pin. Following a
AH
PWM Controller
register enables
BHBL_XOVR
enables cross-
pin.
AL
14-25