Dma Initialization Sequence - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Examples
W[P0] = R1;
ssync; /* NOTE: SPORT0 RX NOT enabled yet (bit 0 of RCR1 must
be zero) */

DMA Initialization Sequence

Next the DMA channels for receive (channel3 in this example) and for
transmit (channel4 in this example) are set up for auto-buffered,
one-dimensional, 32-bit transfers. Again, there are other possibilities, so
generic labels have been used, with a particular value shown in the
comments.
Note that the DMA channels can be enabled at the end of the configura-
tion since the SPORT is not enabled yet. However, if preferred, the user
can enable the DMA later, immediately before enabling the SPORT. The
only requirement is that the DMA channel be enabled before the associ-
ated peripheral is enabled to start the transfer.
Listing 19-2. DMA Initialization
Program_DMA_Controller:
/* Receiver (DMA channel 3) */
/* Set P0 to DMA Base Address */
P0.l = lo(DMA3_CONFIG);
P0.h = hi(DMA3_CONFIG);
/* Configuration (for instance 0x108A for Autobuffer, 32-bit
wide transfers) */
R0 = DMA_RECEIVE_CONF(z);
W[P0] = R0;
/* rx_buf = Buffer in Data memory (divide count by four because
of 32-bit DMA transfers) */
19-72
/* configuration register */
ADSP-BF50x Blackfin Processor Hardware Reference