Pll Overview - Analog Devices ADSP-BF506F Hardware Reference Manual

Phase Locked Loop and Clock Control
DMA Access Bus (DAB), External Access Bus (EAB), and the external bus
interface unit (EBIU).

These buses run at the PLL frequency divided by 1–15 (
domain). Using the
select a divider value that allows these buses to run at or below the
maximum
To optimize performance and power dissipation, the processor allows the
core and system clock frequencies to be changed dynamically in a "coarse
adjustment." For a "fine adjustment," the PLL clock frequency can also be
varied.

PLL Overview

To provide the clock generation for the core and system, the processor
uses an analog PLL with programmable state machine control.
The PLL design serves a wide range of applications. It emphasizes embed-
ded and portable applications and low cost, general-purpose processors, in
which performance, flexibility, and control of power dissipation are key
features. This broad range of applications requires a wide range of fre-
quencies for the clock generation circuitry. The input clock may be a
crystal, a crystal oscillator, or a buffered, shaped clock derived from an
external system clock oscillator.
The PLL interacts with the Dynamic Power Management Controller
(DPMC) block to provide power management functions for the processor.
For information about the DPMC, see
Controller" on page
Subject to the maximum VCO frequency specified in the processor data
sheet, the PLL supports a wide range of multiplier ratios and achieves
multiplication of the input clock,
tion range, the processor uses a combination of programmable dividers in
the PLL feedback circuit and output configuration blocks.
8-2
parameter of the PLL divide register,
SSEL
rate specified in the processor data sheet.
SCLK
8-7.
CLKIN
ADSP-BF50x Blackfin Processor Hardware Reference
"Dynamic Power Management
. To achieve this wide multiplica-
SCLK