Pwm Unit Considerations; Rsi Considerations - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

PWM Unit Considerations

The
PWM0_SYNC
both are configured as
on .
PF7
The
PWM0_TRIP
both are configured as
on .
PF6
If is not selected on either
PWM0_TRIP
signal to the PWM module will be driven low. That is, the
PWM0_TRIP
PWM unit will be tripped if neither of these signals is selected via the
register.
PORTF_MUX
The same principle holds true for the
register.
PORTG_MUX

RSI Considerations

Pull up/pull down enabling for RSI:
• Pull down for
selected on
bit is set in the
• Pull up for
selected on
bit is set in the
• Pull up for
selected on
bit is set in the
• Pull up for
selected on
bit is set in the
9-8
signal appears twice within Port F: on
and selected, inputs will only be enabled
PWM0_SYNC
signal appears twice within Port F: on
and selected, inputs will only be enabled
PWM0_TRIP
will be enabled only if
SD_DATA[3]
(that is,
PG6 PORTG_MUX[9:8]
RSI_CONFIG
will be enabled only if
SD_DATA[3]
(that is,
PG6 PORTG_MUX[9:8]
RSI_CONFIG
will be enabled only if
SD_DATA[0]
(that is,
PG9 PORTG_MUX[11:10]
RSI_CONFIG
will be enabled only if
SD_DATA[1]
(that is,
PG8 PORTG_MUX[9:8]
RSI_CONFIG
ADSP-BF50x Blackfin Processor Hardware Reference
or , then the internal
PF6 PF11
signal on
PWM1_TRIP
==
b#01
register.
==
b#01
register.
==
b#01
register.
==
b#01
register.
and . If
PF7 PF12
and . If
PF6 PF11
, in the
PG5
is
SD_DATA[3]
) and the
PD_Dat3
is
SD_DATA[3]
) and the
PU_Dat3
is
SD_DATA[0]
) and the
PU_Dat
is
SD_DATA[1]
) and the
PU_Dat