Twi Fifo Receive Data Single Byte; Register (Twi_Rcv_Data8); Twi Fifo Receive Data Double Byte; Register (Twi_Rcv_Data16) - Analog Devices ADSP-BF506F Hardware Reference Manual

Register Descriptions

TWI FIFO Receive Data Single Byte

Register (TWI_RCV_DATA8)

The
TWI_RCV_DATA8
buffer. Receive data is read from the corresponding receive buffer in a
first-in first-out order. Although peripheral bus reads are 16 bits, a read
access to
TWI_RCV_DATA8
FIFO buffer. With each access, the receive status (
TWI_FIFO_STAT
FIFO buffer is empty, the data is unknown and the FIFO buffer status
remains indicating it is empty.
TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8)
All bits are RO.
15 14 13 12 11 10
0 0 0 0 0 0
Figure 16-29. TWI FIFO Receive Data Single Byte Register

TWI FIFO Receive Data Double Byte

Register (TWI_RCV_DATA16)

The
TWI_RCV_DATA16
buffer. To reduce interrupt output rates and peripheral bus access times, a
double byte receive data access can be performed. Two data bytes can be
read, effectively emptying the receive FIFO buffer with a single access.
The data is read in little endian byte order as shown in
where byte 0 is the first byte received and byte 1 is the second byte
received. With each access, the receive status (
TWI_FIFO_STAT
16-48
register holds an 8-bit data value read from the FIFO
will access only one transmit data byte from the
register is updated. If an access is performed while the
9 8 7 6 5 4 3
0 0 0 0 0 0 0
register holds a 16-bit data value read from the FIFO
register is updated to indicate it is empty. If an access is
ADSP-BF50x Blackfin Processor Hardware Reference
RCVSTAT
2 1 0
Reset = 0x0000
0 0 0
RCVDATA8[7:0] (Receive
FIFO 8-Bit Data)
RCVSTAT
) field in the
Figure 16-30
) field in the