Clearing the
TSPEN
any ongoing operations. Status bits are also cleared. Configuration bits
remain unaffected and can be read by the software in order to be altered or
overwritten. To disable the SPORT output clock, set the SPORT to be
disabled.
Note that disabling a SPORT via
currently active pulses on the
these signals are configured to be generated internally.
When disabling the SPORT from multichannel operation, first disable
and then disable
TSPEN
abled before re-enabling. Disabling only TX or RX is not allowed.
Setting SPORT Modes
SPORT configuration is accomplished by setting bit and field values in
configuration registers. A SPORT must be configured prior to being
enabled. Once the SPORT is enabled, further writes to the SPORT con-
figuration registers are disabled (except for SPORT_RCLKDIV,
SPORT_TCLKDIV, and multichannel mode channel select registers). To
change values in all other SPORT configuration registers, disable the
SPORT by clearing TSPEN in SPORT_TCR1 and/or RSPEN in
SPORT_RCR1.
Each SPORT has its own set of control registers and data buffers. These
registers are described in detail in
control and status bits in the SPORT registers are active high unless other-
wise noted.
Stereo Serial Operation
Several stereo serial modes can be supported by the SPORT, including the
popular I2S format. To use these modes, set bits in the SPORT_RCR2 or
SPORT_TCR2 registers. Setting RSFSE or TSFSE in SPORT_RCR2 or
ADSP-BF50x Blackfin Processor Hardware Reference
and
enable bits disables the SPORTs and aborts
RSPEN
TFS
. Note both
RSPEN
"SPORT Registers" on page
SPORT Controller
/
may shorten any
TSPEN
RSPEN
/
and
/
RFS
TSCLK
RSCLK
and
TSPEN
RSPEN
outputs, if
must be dis-
19-45. All
19-11
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