Rsi Power Saving Configuration - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description

RSI Power Saving Configuration

The RSI requires two internal clock signals that are derived directly from
. In order for the RSI to function, these clocks must be enabled via
SCLK
in the
RSI_CLK_EN
RSI regardless of the other RSI clock configurations. One of these clock
signals is routed to the clock divider and generates the clock that is pro-
vided on the
RSI_CLK
disabled via
CLK_EN
ture is implemented via
output when there are no transfers taking place on the RSI inter-
RSI_CLK
face, providing additional power saving options.
Table 21-3. RSI Power Saving Configurations
CLKS_EN CLK_EN PWR_SV_E
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
1 The PWR_ON field of the
If PWR_ON is 0x0, the clock will not be output.
21-14
register. Clearing
RSI_CONFIG
signal. The
RSI_CLK
in the
RSI_CLK_CONTROL
that allows for the disabling of the
PWR_SV_EN
RSI State
0 Disabled
1 Disabled
0 Disabled
1 Disabled
0 Enabled
1 Enabled
0 Enabled
1 Enabled
register must be set to 0x3.
RSI_PWR_CTL
ADSP-BF50x Blackfin Processor Hardware Reference
RSI_CLK_EN
signal can be enabled or
register and a power save fea-
RSI_CLK output
No clock
No clock
No clock
No clock
No clock
No clock
1
Continuous clock
Clock only driven during transfers
disables the
1