Analog Devices ADSP-BF506F Hardware Reference Manual page 547

PWM
CONFIGURATION
REGISTERS
PWM_TM
PAB BUS
PWM_CTRL
Figure 14-1. PWM Controller Block Diagram
• PWM Shutdown & Interrupt Control Unit. This block takes care
of the various PWM shutdown modes (via the
the
PWM_CTRL
for the Three-Phase PWM Timing Unit and interrupt signals for
the Interrupt Control Unit
• PWM Sync Pulse Control Unit. This block generates the internal
PWM synchronization pulse and also controls whether an external
PWM_SYNC
ADSP-BF50x Blackfin Processor Hardware Reference
PWM DUTY
CYCLE
REGISTERS
PWM_CHA
PWM_DT
PWM_CHB
PWM_SEG[8:6]
PWM_CHC
DEAD
THREE-PHASE
TIME
PWM TIMING
CONTROL
UNIT
UNIT
SYNC SR RESET
PWM_SYNCWT
PWM
SYNC PULSE
CONTROL
UNIT
register). This unit generates the correct reset signal
pulse is used.
PWM_STAT2
PWM_SEG[5:0] PWM_GATE
OUTPUT
CONTROL
UNIT
SYNC
CLK
PWM_SRMODE
PWM_POLARITY
PWM
SHUTDOWN
AND INTERRUPT
CONTROL
UNIT
PWM_TRIP
PWM Controller
PWM_AH
PWM_AL
GATE
PWM_BH
DRIVE
PWM_BL
UNIT
PWM_CH
PWM_CL
SR POL CLK
CLK
PWM_TRIPB
FIO_COMP_TRIPB
PWM_TRIP_IRQ
PWM_SYNC_IRQ
RESETB
pin and
14-3