Analog Devices ADSP-BF506F Hardware Reference Manual page 1035

RSI Data Control Register (RSI_DATA_CONTROL)
Read/Write
15 14 13 12 11 10
0xFFC0 382C
0
Reserved
CEATA_CCS_EN
CEATA_EN
Figure 21-14. RSI Data Control Register
Table 21-18. RSI_DATA_CONTROL Register
Bit Name
0 DATA_EN
1 DATA_DIR
2 DATA_MODE
3 DATA_DMA_EN
7:4 DATA_BLK_LGTH
8 CEATA_EN
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7
0 0 0 0 0 0 0 0
Function
Data enable
0 = Disabled (disables data path
state machine)
1 = Enabled (enables data path
state machine)
Data transfer direction
0 = From RSI to card
1 = From card to RSI
Data transfer mode
0 = Block transfer
1 = Stream transfer
Data DMA enable
0 = Disabled (use core to
read/write RSI_FIFO)
1 = Enabled (use DMA controller
to read/write RSI_FIFO)
Data block length
0x0 - 0xC
data block length (2
CE-ATA mode enable
0 = Disabled
1 = Enabled
Removable Storage Interface
6 5 4 3 2 1 0
0 0 0 0 0 0 0
0 12
to 2 )
Reset = 0x0000
DATA_EN
DATA_DIR
DATA_MODE
DATA_DMA_EN
DATA_BLK_LGTH
Type Default
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
21-63