Pwm Operating Mode (Pwm_Ctrl And Pwm_Stat); (Pwm_Cha, Pwm_Chb, And Pwm_Chc) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

PWM Operating Mode (PWM_CTRL and PWM_STAT)

Registers
The PWM Controller can operate in two distinct modes: single-update
mode and double-update mode. The mode is determined by the state of
bit of the
PWM_DBL
Controller operates in single-update mode. Setting the
the PWM Controller in double-update mode. Following a peripheral reset
or power on, the
defaults to single-update mode.
In single-update mode, a
period. The rising edge of this signal marks the start of a new PWM cycle
and is used to latch new values from the PWM configuration registers
( ,
PWM_TM PWM_DT
( ,
PWM_CHA PWM_CHB
Three-Phase PWM Timing Unit. In addition, the
latched into the Output Control Unit on the rising edge of the
pulse. In effect, this means that the characteristics and resultant duty
cycles of the PWM signals can be updated only once per PWM period at
the start of each cycle. This results in PWM patterns that are symmetrical
about the midpoint of the switching period.
In double-update mode, an additional
midpoint of each PWM period. The rising edge of this second
pulse is again used to latch new values of the PWM configuration regis-
ters, duty cycle registers, and the
to alter both the characteristics (switching frequency, dead time, and
pulse width) and the output duty cycles at the midpoint of each
PWM_SYNC
PWM cycle. Consequently, it is possible to produce PWM switching pat-
terns that are no longer symmetrical about the midpoint of the period
(asymmetrical PWM patterns).
In double-update mode, it may be necessary to know whether operation at
any point in time is in the first or second half of the PWM cycle. This
ADSP-BF50x Blackfin Processor Hardware Reference
register. When this bit is cleared, the PWM
PWM_CTRL
bit is cleared; thus, PWM Controller operation
PWM_DBL
PWM_SYNC
, and ), and the PWM duty cycle registers
PWM_SYNCWT
, ,
PWM_CHC PWM_CHAL
PWM_SEG
pulse is produced during each PWM
, , and
PWM_CHBL
PWM_SEG
pulse is produced at the
PWM_SYNC
register. As a result, it is possible
PWM Controller
bit places
PWM_DBL
) into the
PWM_CHCL
register is also
PWM_SYNC
PWM_SYNC
14-13