Analog Devices ADSP-BF506F Hardware Reference Manual page 841

Figure 18-13 provides the bit descriptions for
SPI Control Register (SPI_CTL)
15 14 13 12 11 10
0 0
SPE (SPI Enable)
0 - Disabled
1 - Enabled
WOM (Write Open Drain
Master)
0 - Normal
1 - Open drain
MSTR (Master)
Sets the SPI module as
master or slave
0 - Slave
1 - Master
CPOL (Clock Polarity)
0 - Active high SCK
1 - Active low SCK
CPHA (Clock Phase)
Selects transfer format and
operation mode
0 - SCK toggles from middle
of the first data bit, slave select
pins controlled by hardware
1 - SCK toggles from beginning
of first data bit, slave select
pins controlled by software
LSBF (LSB First)
0 - MSB sent/received first
1 - LSB sent/received first
SIZE (Size of Words)
0 - 8 bits
1 - 16 bits
Figure 18-13. SPI Control Register
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7 6
0 0 0 1 0 0 0 0
SPI-Compatible Port Controller
SPI_CTL
5 4 3 2 1 0
0 0 0 0 0 0 Reset = 0x0400
TIMOD[1:0] (Transfer Initiation
Mode)
00 - Start transfer with read of
SPI_RDBR, interrupt when
SPI_RDBR is full
01 - Start transfer with write of
SPI_TDBR, interrupt when
SPI_TDBR is empty
10 - Start transfer with DMA read
of SPI_RDBR, request further
DMA reads as long as SPI DMA
FIFO is not empty
11 - Start transfer with DMA write
of SPI_TDBR, request further
DMA writes as long as SPI DMA
FIFO is not full
SZ (Send Zero)
Send zero or last word when
SPI_TDBR is empty
0 - Send last word
1 - Send zeros
GM (Get More Data)
When SPI_RDBR is full, get
data or discard incoming data
0 - Discard incoming data
1 - Get more data, overwrite
previous data
PSSE (Slave Select Enable)
0 - Disable
1 - Enable
EMISO (Enable MISO)
0 - MISO disabled
1 - MISO enabled
.
18-37