Descriptor-Based Dma Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Modes of Operation

Descriptor-based DMA Operation

In descriptor-based DMA operation, software does not set up DMA
sequences by writing directly into DMA controller registers. Rather, soft-
ware keeps DMA configurations, called descriptors, in memory. On
demand, the DMA controller loads the descriptor from memory and over-
writes the affected DMA registers by its own control. Descriptors can be
fetched from L1 memory using the DCB bus or from external memory
using the DEB bus.
A descriptor describes what kind of operation should be performed next
by the DMA channel. This includes the DMA configuration word as well
as data source/destination address, transfer count, and address modify val-
ues. A DMA sequence controlled by one descriptor is called a work unit.
Optionally, an interrupt can be requested at the end of any work unit by
setting the
DI_EN
descriptor.
A DMA channel is started in descriptor-based mode by first writing the
32-bit address of the first descriptor into the
(or the
DMAx_CURR_DESC_PTR
performing a write to the
either 0x4, 0x6, or 0x7 and enables the
controller to immediately fetch the descriptor from the address pointed to
by the
DMAx_NEXT_DESC_PTR
register again. If the
processing.
The bit in the
DFETCH
fetch is ongoing on the respective DMA channel. The
DMAx_CURR_DESC_PTR
next.
7-14
bit in the configuration word of the respective
in case of descriptor array mode) and then
DMAx_CONFIG
register. The fetch overwrites the
bit is still set, the channel starts DMA
DMAEN
DMAx_IRQ_STATUS
points to the descriptor value that is to be fetched
ADSP-BF50x Blackfin Processor Hardware Reference
DMAx_NEXT_DESC_PTR
register that sets the
bit. This causes the DMA
DMAEN
register tells whether a descriptor
register
field to
FLOW
DMAx_CONFIG