Analog Devices ADSP-BF506F Hardware Reference Manual page 623

The bit controls how many stop bits are appended to transmitted
STB
data. When
STB=0
instructs the transmitter to add one additional stop bit, two stop bits in
total. If
WLS=0
to append one additional half bit, 1 1/2 stop bits in total. Note that this
bit does not impact data reception—the receiver is always satisfied with
one stop bit.
The bit inserts one additional bit between the most significant data bit
PEN
and the first stop bit. The polarity of this so-called parity bit depends on
data and the
STP
late the parity value. The receiver compares the received parity bit with
the expected value and issues a parity error if they don't match. If
cleared, the
STP
The bit controls whether the parity is generated by hardware based on
STP
the data bits or whether it is set to a fixed value. If
culates the parity bit value based on the data bits. Then, the
determines whether odd or even parity mode is chosen. If
ity is used. That means that the total count of
including the parity bit must be an odd value. Even parity is chosen by
and
STP=0 EPS=1
If the bit is set, then hardware parity calculation is disabled. In this
STP
case, the sent and received parity equals the inverted
in Table 15-5
( ).
WLS=3
Table 15-5. UART Parity
PEN STP
0 x
1 0
1 0
1 0
ADSP-BF50x Blackfin Processor Hardware Reference
, one stop bit is transmitted. If
and 5-bit operation is chosen,
and control bits. Both transmitter and receiver calcu-
EPS
and the bits are ignored.
EPS
. Then, the count of
summarizes polarity behavior assuming 8-bit data words
EPS Data (hex)
x x
0 0x60
0 0x57
1 0x60
UART Port Controllers
is non zero,
WLS
forces the transmitter
STB=1
STP=0
logical–1
bits must be a even value.
logical–1
EPS
Data (binary, LSB
first)
x
0000 0110
1110 1010
0000 0110
STB=1
is
PEN
the hardware cal-
bit
EPS
, odd par-
EPS=0
data bits
bit. The example
Parity
None
1
0
0
15-29