Unique Information For The Adsp-Bf50X Processor - Analog Devices ADSP-BF506F Hardware Reference Manual

Unique Information for the ADSP-BF50x Processor

debug operation. Bit diagrams and descriptions are provided in
Figure 14-24 and
PWM Simulation Status Register (PWM_STAT2)
15 14 13 12 11 10
0 0
Reserved
Figure 14-24. PWM Simulation Status Register
Table 14-18. PWM_STAT2 Register
Bit Name
0 PWM_AL
1 PWM_AH
2 PWM_BL
3 PWM_BH
4 PWM_CL
5 PWM_CH
15:6 Reserved
Unique Information for the ADSP-BF50x
Processor
None.
14-50
Table 14-18.
9 8 7 6
0 0 0 0 0 0 0 0
Function
PWM_AL output signal for S/W observation
PWM_AH output signal for S/W observation
PWM_BL output signal for S/W observation
PWM_BH output signal for S/W observation
PWM_CL output signal for S/W observation
PWM_CH output signal for S/W observation
ADSP-BF50x Blackfin Processor Hardware Reference
5 4 3 2 1 0
0 0 0 0 0 0
PWM_AL
PWM_AH
PWM_BL
PWM_BH
PWM_CL
PWM_CH
Reset = 0x0000
Type Default
RO 0
RO 0
RO 0
RO 0
RO 0
RO 0
0