Analog Devices ADSP-BF506F Hardware Reference Manual page 635

UART Interrupt Enable Clear Registers (UARTx_IER_CLEAR)
15 14 13 12 11 10
For memory-
0 0
mapped
addresses,
see Table 15-12.
ERFCI (Enable Receive FIFO Count Interrupt)
0 - No interrupt
1 - Generate status interrupt if RFCS
bit in UARTx_MSR is set
ETFI (Enable Transmission Finished Interrupt)
0 - No interrupt
1 - Generate status interrupt if
TFI bit in UARTx_LSR is set
Unused
EDSSI (Enable Modem Status Interrupt)
0 - No interrupt
1 - Generate status interrupt
if SCTS bit in UARTx_MSR is set
Figure 15-15. UART Interrupt Enable Clear Registers
Table 15-12. UART Interrupt Enable Clear Register Memory-Mapped
Addresses
Register Name
UART0_IER_CLEAR
UART1_IER_CLEAR
The UART's DMA is enabled by first setting up the system DMA control
registers and then enabling the UART
the
UARTx_IER
as DMA request lines. Depending on whether DMA is enabled or not,
upon receiving these requests, the DMA control unit either generates a
direct memory access or passes the UART interrupt on to the system inter-
rupt handling unit. However, UART's error interrupt goes directly to the
system interrupt handling unit, bypassing the DMA unit completely.
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7
0 0 0 0 0 0 0
Memory-Mapped Address
0xFFC0 0424
0xFFC0 2024
register. This is because the interrupt request lines double
UART Port Controllers
6 5 4 3 2 1 0
0 0 0 0 0 0 0
ERBFI (Enable Receive Buf-
fer Full Interrupt)
ELSI (Enable RX Status
Interrupt)
0 - No interrupt
1 - Generate status interrupt
and/or
ERBFI
Reset = 0x0000
0 - No interrupt
1 - Generate RX interrupt if
DR bit in UARTx_LSR is
set
ETBEI (Enable Transmit
Buffer Empty Interrupt)
0 - No interrupt
1 - Generate TX interrupt if
THRE bit in UARTx_LSR is
set
if any of UARTx_LSR[4:1]
is set
interrupts in
ETBEI
15-41