Internal Pwm Sync Generation; External Pwm Sync Generation - Analog Devices ADSP-BF506F Hardware Reference Manual

Internal PWM SYNC Generation

The PWM Controller produces an output PWM synchronization pulse at
a rate equal to the PWM switching frequency in single-update mode and
at twice the PWM frequency in double-update mode. This pulse is avail-
able for external use at the
pulse is programmable by the 10-bit read/write
width of the PWM SYNC pulse (
T
so that the width of the pulse is programmable from t
(corresponding to 10 ns to 10.24
Following a reset, the
so that the default
100 MHz.

External PWM SYNC Generation

By setting the
PWM_EXTSYNC
in a mode to expect an external PWM SYNC on the
external sync should be synchronized by setting the
register to 0, which assumes the selected external PWM SYNC is
PWM_CTRL
asynchronous.
The external PWM SYNC period is expected to be an integer multiple of
the internal PWM SYNC period. When the rising edge of the external
is detected, the PWM Controller is restarted at the beginning of
PWM_SYNC
the PWM cycle. If the external PWM SYNC period is not an integer mul-
tiple of the internal PWM SYNC, the behavior of the PWM channel
outputs will be clipping. Note that a small amount of jitter inherent in the
synchronization logic cannot be avoided when the external PWM SYNC
is synchronized.
ADSP-BF50x Blackfin Processor Hardware Reference
PWM_SYNC
=
t
PWMSYNC SCLK
PWM_SYNCWT
width is 10.24
PWM_SYNC
bit of the
pin. The width of this PWM SYNC
PWM_SYNCWT
) is given by:
TPWM_SYNC
 
PWMSYNCWT

s for an f rate of 100 MHz).
SCLK
register contains 0x3FF (1023 decimal)

s, again for an f
register, the PWM is set up
PWM_CTRL
PWM_SYNCSEL
PWM Controller
register. The

+
1
to 1024*t
SCLK SCLK
of
SCLK
pin. The
PWM_SYNC
bit of the
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