Twi Master Mode Status Register (Twi_Master_Stat) - Analog Devices ADSP-BF506F Hardware Reference Manual

TWI Master Mode Status Register
(TWI_MASTER_STAT)

TWI Master Mode Status Register (TWI_MASTER_STAT)

15 14 13 12 11 10
0 0 0 0
BUSBUSY (Bus Busy) - RO
SCLSEN (Serial Clock Sense) - RO
SDASEN (Serial Data Sense) - RO
BUFWRERR (Buffer Write Error) - W1C
BUFRDERR (Buffer Read Error) - W1C
Figure 16-21. TWI Master Mode Status Register
The
TWI_MASTER_STAT
transfers and at their conclusion. Generally, master mode status bits are
not directly associated with the generation of interrupts but offer informa-
tion on the current transfer. Slave mode operation does not affect master
mode status bits.
Note that—while the
pull-up resistor on
edge bits (
ANAK
acknowledge conditions are sampled during the high phase of
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7 6 5
0 0 0 0 0 0 0
register holds information during master mode
bit is set (this could be due to having no
SCLSEN
or another agent is driving
SCL
and ) do not update. This result occurs because the
DNAK
Two-Wire Interface Controller
4 3 2 1 0
0 0 0 0 0 Reset = 0x0000
MPROG (Master Transfer
in Progress) - RO
LOSTARB (Lost Arbitration) -
W1C
ANAK (Address Not
Acknowledged) - W1C
DNAK (Data Not
Acknowledged) - W1C
SCL
low)—the acknowl-
.
SCL
16-35