Peripheral Access Bus (Pab) - Analog Devices ADSP-BF506F Hardware Reference Manual

INT
ACK CORE
EVENT
CONTROLLER
RESET
VECTOR
CORE TIMER
32 32
DMA CORE BUS
(DCB)
Figure 3-2. Core Block Diagram

Peripheral Access Bus (PAB)

The processor has a dedicated low latency peripheral bus that keeps core
stalls to a minimum and allows for manageable interrupt latencies to
time-critical peripherals. All peripheral resources accessed through the
PAB are mapped into the system MMR space of the processor memory
map. The core accesses system MMR space through the PAB bus.
ADSP-BF50x Blackfin Processor Hardware Reference
JTAG
DEBUG AND JTAG INTERFACE
PROCESSOR
32 32
L1 DATA
Chip Bus Hierarchy
DSP ID
(8 BITS)
32 32 64
MEMORY
MANAGEMENT
UNIT
EAB
SYSTEM CLOCK
AND POWER
MANAGEMENT
POWER AND
CLOCK
CONTROLLER
PERFORMANCE
MONITOR
CORE
L1 INSTRUCTION
PAB
3-5