Analog Devices ADSP-BF506F Hardware Reference Manual page 1002

Functional Description
the flag upon starting a data transmit operation. During the data
TX_ACT
transfer, the transmit logic maintains a number of transmit FIFO status
flags as shown in
Table 21-9. RSI Transmit FIFO Status Flags
RSI_STATUS Flag
TX_FIFO_STAT
TX_FIFO_FULL
TX_FIFO_EMPTY
TX_UNDERRUN
TX_DAT_RDY
When the receive FIFO is disabled, all receive status flags are deasserted
and the receive read and write pointers are reset. The RSI asserts the
flag upon starting a data read transaction. During the data transfer,
RX_ACT
the receive logic maintains the receive FIFO status flags shown in
Table 21-10.
Table 21-10. RSI Receive FIFO Status Flags
RSI_STATUS Flag
RX_FIFO_STAT
RX_FIFO_FULL
RX_FIFO_EMPTY
RX_OVERRUN
RX_DAT_RDY
21-30
Table 21-9.
Description
Transmit FIFO is half empty
Transmit FIFO is full
Transmit FIFO is empty
Transmit FIFO under run error
Valid data available in the transmit FIFO
Description
Receive FIFO is half empty
Receive FIFO is full
Receive FIFO is empty
Receive FIFO under run error
Valid data available in the receive FIFO
ADSP-BF50x Blackfin Processor Hardware Reference