Analog Devices ADSP-BF506F Hardware Reference Manual page 865

SPORT Controller
The primary and secondary data pins, if enabled by a specific processor
port configuration, provide a method to increase the data throughput of
the serial port. They do not behave as totally separate SPORTs; rather,
they operate in a synchronous manner (sharing clock and frame sync) but
on separate data. The data received on the primary and secondary signals
is interleaved in main memory and can be retrieved by setting a stride in
the data address generators (DAG) unit. For more information about
DAGs, see the Data Address Generators chapter in Blackfin Processor Pro-
gramming Reference. Similarly, for TX, data should be written to the TX
register in an alternating manner—first primary, then secondary, then pri-
mary, then secondary, and so on. This is easily accomplished with the
processor's powerful DAGs.
In addition to the serial clock signal, data must be signalled by a frame
synchronization signal. The framing signal can occur either at the begin-
ning of an individual word or at the beginning of a block of words.
Figure 19-2 shows a possible port connection for a device with at least two
SPORTs. Note serial devices A and B must be synchronous, as they share
common frame syncs and clocks. The same is true for serial devices 1, 2,
...N.
ADSP-BF50x Blackfin Processor Hardware Reference 19-7