Analog Devices ADSP-BF506F Hardware Reference Manual page 674

Programming Model
WRITE TWI_MASTER_CTL WITH COUNT,
MDIR SET, AND MEN SET. THIS
STARTS THE TRANSFER
WAIT FOR INTERRUPTS
RCVSERV
INTERRUPT
SOURCE
READ DATA FROM
TWI_RCV_DATA
REGISTER
WRITE TWI_INT_STAT
TO CLEAR INTERRUPT
Figure 16-13. TWI Master Mode
16-24
WRITE TO TWI_CONTROL TO SET
PRESCALE AND ENABLE THE TWI
WRITE TO TWI_CLK_DIV
WRITE TO TWI_MASTER_ADDR WITH THE
ADDRESS OF THE TARGETED DEVICE
WRITE TO TWI_FIFO_CTL TO SELECT WHETHER
1 OR 2 BYTES GENERATE INTERRUPTS
WRITE TO TWI_INT_MASK TO UNMASK
TWI EVENTS TO GENERATE INTERRUPTS
RECEIVE
TRANSFER
DIRECTION
MCOMP
WRITE TWI_INT_STAT
TO CLEAR INTERRUPT
MERR
DONE
READ TWI_MASTER_STAT TO GET ERROR CAUSE
HANDLE ERROR AS APPROPRIATE AND W1C THE
CORRESPONDING BIT IN TWI_MASTER_STAT
WRITE TWI_INT_STAT TO CLEAR MERR BIT
WAIT FOR INTERRUPTS
ADSP-BF50x Blackfin Processor Hardware Reference
WRITE TWI_MASTER_CTL WITH COUNT,
TRANSMIT
MDIR CLEARED, AND MEN SET. THIS
STARTS THE TRANSFER
WAIT FOR INTERRUPTS
MCOMP
INTERRUPT
SOURCE
MERR
WRITE DATA INTO
WRITE TWI_INT_STAT
TO CLEAR INTERRUPT
XMTSERV
TWI_XMT_DATA
REGISTER